Sanjay Patel 58b6a4e3f2 [InstCombine] prefer xor with -1 because 'not' is easier to understand (PR32706) ... This matches the demanded bits behavior in the DAG and should fix: https://bugs.llvm.org/show_bug.cgi?id=32706 Differential Revision: https://reviews.llvm.org/D32255 llvm-svn: 300977		2017-04-21 14:03:54 +00:00
..
CMakeLists.txt
InstCombineAddSub.cpp	[APInt] Rename getSignBit to getSignMask	2017-04-20 16:56:25 +00:00
InstCombineAndOrXor.cpp	[APInt] Rename getSignBit to getSignMask	2017-04-20 16:56:25 +00:00
InstCombineCalls.cpp	Simplify test for sret attribute in instcombine	2017-04-19 23:17:47 +00:00
InstCombineCasts.cpp	Add a getPointerOperandType() helper to LoadInst and StoreInst; NFC	2017-04-18 22:00:54 +00:00
InstCombineCompares.cpp	[APInt] Rename getSignBit to getSignMask	2017-04-20 16:56:25 +00:00
InstCombineInternal.h	[InstCombine] function names start with lower-case letter; NFC	2017-04-20 22:37:01 +00:00
InstCombineLoadStoreAlloca.cpp	[InstCombine] Reduce visitLoadInst() code duplication. NFCI.	2017-04-19 17:26:57 +00:00
InstCombineMulDivRem.cpp	[APInt] Rename getSignBit to getSignMask	2017-04-20 16:56:25 +00:00
InstCombinePHI.cpp	[InstCombine] Support folding a subtract with a constant LHS into a phi node	2017-04-14 19:20:12 +00:00
InstCombineSelect.cpp	[APInt] Rename getSignBit to getSignMask	2017-04-20 16:56:25 +00:00
InstCombineShifts.cpp	[APInt] Rename getSignBit to getSignMask	2017-04-20 16:56:25 +00:00
InstCombineSimplifyDemanded.cpp	[InstCombine] prefer xor with -1 because 'not' is easier to understand (PR32706)	2017-04-21 14:03:54 +00:00
InstCombineVectorOps.cpp	InstCombine: Use the InstSimplify hook for shufflevector	2017-04-04 04:47:57 +00:00
InstructionCombining.cpp	[APInt] Cast calls to add/sub/mul overflow methods to void if only their overflow bool out param is used.	2017-04-19 21:09:45 +00:00
LLVMBuild.txt