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66 lines
2.3 KiB
C++
66 lines
2.3 KiB
C++
//===-- X86TargetMachine.h - Define TargetMachine for the X86 ---*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares the X86 specific subclass of TargetMachine.
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//
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//===----------------------------------------------------------------------===//
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#ifndef X86TARGETMACHINE_H
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#define X86TARGETMACHINE_H
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetFrameInfo.h"
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#include "llvm/PassManager.h"
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#include "X86InstrInfo.h"
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#include "X86JITInfo.h"
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namespace llvm {
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class IntrinsicLowering;
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class X86TargetMachine : public TargetMachine {
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X86InstrInfo InstrInfo;
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TargetFrameInfo FrameInfo;
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X86JITInfo JITInfo;
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public:
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X86TargetMachine(const Module &M, IntrinsicLowering *IL);
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virtual const X86InstrInfo &getInstrInfo() const { return InstrInfo; }
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virtual const TargetFrameInfo &getFrameInfo() const { return FrameInfo; }
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virtual TargetJITInfo *getJITInfo() { return &JITInfo; }
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virtual const MRegisterInfo *getRegisterInfo() const {
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return &InstrInfo.getRegisterInfo();
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}
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// deprecated interfaces
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virtual const TargetSchedInfo &getSchedInfo() const { abort(); }
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virtual const TargetRegInfo &getRegInfo() const { abort(); }
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/// addPassesToEmitMachineCode - Add passes to the specified pass manager to
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/// get machine code emitted. This uses a MachineCodeEmitter object to handle
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/// actually outputting the machine code and resolving things like the address
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/// of functions. This method should returns true if machine code emission is
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/// not supported.
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///
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virtual bool addPassesToEmitMachineCode(FunctionPassManager &PM,
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MachineCodeEmitter &MCE);
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virtual bool addPassesToEmitAssembly(PassManager &PM, std::ostream &Out);
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};
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// this is implemented in X86CodeEmitter.cpp
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namespace X86 {
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void emitInstruction(MachineCodeEmitter& mce,
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const X86InstrInfo& ii,
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const MachineInstr& MI);
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}
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} // End llvm namespace
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#endif
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