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llvm-mirror/test/CodeGen
Sanjay Patel fa4a9158e9 fix invalid load folding with SSE/AVX FP logical instructions (PR22371)
This is a follow-up to the FIXME that was added with D7474 ( http://reviews.llvm.org/rL229531 ).
I thought this load folding bug had been made hard-to-hit, but it turns out to be very easy
when targeting 32-bit x86 and causes a miscompile/crash in Wine:
https://bugs.winehq.org/show_bug.cgi?id=38826
https://llvm.org/bugs/show_bug.cgi?id=22371#c25

The quick fix is to simply remove the scalar FP logical instructions from the load folding table
in X86InstrInfo, but that causes us to miss load folds that should be possible when lowering fabs,
fneg, fcopysign. So the majority of this patch is altering those lowerings to use *vector* FP
logical instructions (because that's all x86 gives us anyway). That lets us do the load folding 
legally.

Differential Revision: http://reviews.llvm.org/D11477

llvm-svn: 243361
2015-07-28 00:48:32 +00:00
..
AArch64 [AArch64] Remove check for Darwin that was needed to decide if x18 should 2015-07-27 19:18:47 +00:00
AMDGPU AMDGPU: don't match vgpr loads for constant loads 2015-07-27 18:16:08 +00:00
ARM DI/Verifier: Fix argument bitrot in DILocalVariable 2015-07-24 23:59:25 +00:00
BPF
CPP
Generic DI/Verifier: Fix argument bitrot in DILocalVariable 2015-07-24 23:59:25 +00:00
Hexagon
Inputs
Mips
MIR MIR Serialization: Serialize the unnamed basic block references. 2015-07-27 22:42:41 +00:00
MSP430
NVPTX [BranchFolding] do not iterate the aliases of virtual registers 2015-07-22 04:16:52 +00:00
PowerPC Fix PPCMaterializeInt to check the size of the integer based on the 2015-07-25 00:48:08 +00:00
SPARC
SystemZ
Thumb [ARM] Make the frame lowering code ready for shrink-wrapping. 2015-07-22 16:34:37 +00:00
Thumb2 ARMLoadStoreOptimizer: Create LDRD/STRD on thumb2 2015-07-21 00:18:59 +00:00
WebAssembly WebAssembly: add a generic CPU 2015-07-27 23:25:54 +00:00
WinEH
X86 fix invalid load folding with SSE/AVX FP logical instructions (PR22371) 2015-07-28 00:48:32 +00:00
XCore