Jessica Paquette c5bda355e6 [GlobalISel][AArch64] Don't emit cset for G_FCMPs feeding into G_BRCONDs ... Similar to the FP case in `AArch64TargetLowering::LowerBR_CC`. Instead of emitting the csets + a tbnz, just emit a compare + bcc (or two bccs, depending on the condition code) This improves cases like this: https://godbolt.org/z/v8hebx This is a 0.1% geomean code size improvement for CTMark at -O3. Differential Revision: https://reviews.llvm.org/D88624		2020-10-01 15:34:16 -07:00
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AArch64CallLowering.cpp	AArch64/GlobalISel: Narrow stack passed argument access size	2020-09-25 13:35:17 -04:00
AArch64CallLowering.h	[SVE][CodeGen] Fix bug when falling back to DAG ISel	2020-07-07 09:23:04 +01:00
AArch64InstructionSelector.cpp	[GlobalISel][AArch64] Don't emit cset for G_FCMPs feeding into G_BRCONDs	2020-10-01 15:34:16 -07:00
AArch64LegalizerInfo.cpp	[AArch64][GlobalISel] Alias rules for G_FCMP to G_ICMP.	2020-10-01 15:20:09 -07:00
AArch64LegalizerInfo.h	[AArch64][GlobalISel] Use custom legalization for G_TRUNC for v8i8 vectors.	2020-10-01 13:22:00 -07:00
AArch64PostLegalizerCombiner.cpp	[AArch64][GlobalISel] Add a post-legalize combine for lowering vector-immediate G_ASHR/G_LSHR.	2020-09-21 16:04:52 -07:00
AArch64PreLegalizerCombiner.cpp	GlobalISel: Add generic instructions for memory intrinsics	2020-08-26 20:08:45 -04:00
AArch64RegisterBankInfo.cpp	[AArch64][GlobalISel] Infer whether G_PHI is going to be a FPR in regbankselect	2020-09-28 10:37:09 -07:00
AArch64RegisterBankInfo.h	[AArch64][GlobalISel] Infer whether G_PHI is going to be a FPR in regbankselect	2020-09-28 10:37:09 -07:00