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55e119a4fc
Fixes https://bugs.llvm.org/show_bug.cgi?id=40805 introduced by patterns added in D53676. I'm removing the patterns entirely here, as they are not correct in the general case. If necessary something more specific can be added in the future. Differential Revision: https://reviews.llvm.org/D58575 llvm-svn: 354733
124 lines
6.0 KiB
TableGen
124 lines
6.0 KiB
TableGen
// WebAssemblyInstrInteger.td-WebAssembly Integer codegen -------*- tablegen -*-
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// WebAssembly Integer operand code-gen constructs.
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///
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//===----------------------------------------------------------------------===//
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multiclass UnaryInt<SDNode node, string name, bits<32> i32Inst,
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bits<32> i64Inst> {
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defm _I32 : I<(outs I32:$dst), (ins I32:$src), (outs), (ins),
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[(set I32:$dst, (node I32:$src))],
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!strconcat("i32.", !strconcat(name, "\t$dst, $src")),
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!strconcat("i32.", name), i32Inst>;
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defm _I64 : I<(outs I64:$dst), (ins I64:$src), (outs), (ins),
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[(set I64:$dst, (node I64:$src))],
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!strconcat("i64.", !strconcat(name, "\t$dst, $src")),
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!strconcat("i64.", name), i64Inst>;
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}
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multiclass BinaryInt<SDNode node, string name, bits<32> i32Inst,
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bits<32> i64Inst> {
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defm _I32 : I<(outs I32:$dst), (ins I32:$lhs, I32:$rhs), (outs), (ins),
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[(set I32:$dst, (node I32:$lhs, I32:$rhs))],
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!strconcat("i32.", !strconcat(name, "\t$dst, $lhs, $rhs")),
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!strconcat("i32.", name), i32Inst>;
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defm _I64 : I<(outs I64:$dst), (ins I64:$lhs, I64:$rhs), (outs), (ins),
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[(set I64:$dst, (node I64:$lhs, I64:$rhs))],
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!strconcat("i64.", !strconcat(name, "\t$dst, $lhs, $rhs")),
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!strconcat("i64.", name), i64Inst>;
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}
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multiclass ComparisonInt<CondCode cond, string name, bits<32> i32Inst, bits<32> i64Inst> {
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defm _I32 : I<(outs I32:$dst), (ins I32:$lhs, I32:$rhs), (outs), (ins),
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[(set I32:$dst, (setcc I32:$lhs, I32:$rhs, cond))],
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!strconcat("i32.", !strconcat(name, "\t$dst, $lhs, $rhs")),
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!strconcat("i32.", name), i32Inst>;
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defm _I64 : I<(outs I32:$dst), (ins I64:$lhs, I64:$rhs), (outs), (ins),
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[(set I32:$dst, (setcc I64:$lhs, I64:$rhs, cond))],
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!strconcat("i64.", !strconcat(name, "\t$dst, $lhs, $rhs")),
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!strconcat("i64.", name), i64Inst>;
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}
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// The spaces after the names are for aesthetic purposes only, to make
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// operands line up vertically after tab expansion.
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let isCommutable = 1 in
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defm ADD : BinaryInt<add, "add ", 0x6a, 0x7c>;
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defm SUB : BinaryInt<sub, "sub ", 0x6b, 0x7d>;
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let isCommutable = 1 in
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defm MUL : BinaryInt<mul, "mul ", 0x6c, 0x7e>;
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// Divide and remainder trap on a zero denominator.
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let hasSideEffects = 1 in {
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defm DIV_S : BinaryInt<sdiv, "div_s", 0x6d, 0x7f>;
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defm DIV_U : BinaryInt<udiv, "div_u", 0x6e, 0x80>;
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defm REM_S : BinaryInt<srem, "rem_s", 0x6f, 0x81>;
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defm REM_U : BinaryInt<urem, "rem_u", 0x70, 0x82>;
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} // hasSideEffects = 1
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let isCommutable = 1 in {
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defm AND : BinaryInt<and, "and ", 0x71, 0x83>;
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defm OR : BinaryInt<or, "or ", 0x72, 0x84>;
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defm XOR : BinaryInt<xor, "xor ", 0x73, 0x85>;
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} // isCommutable = 1
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defm SHL : BinaryInt<shl, "shl ", 0x74, 0x86>;
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defm SHR_S : BinaryInt<sra, "shr_s", 0x75, 0x87>;
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defm SHR_U : BinaryInt<srl, "shr_u", 0x76, 0x88>;
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defm ROTL : BinaryInt<rotl, "rotl", 0x77, 0x89>;
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defm ROTR : BinaryInt<rotr, "rotr", 0x78, 0x8a>;
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let isCommutable = 1 in {
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defm EQ : ComparisonInt<SETEQ, "eq ", 0x46, 0x51>;
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defm NE : ComparisonInt<SETNE, "ne ", 0x47, 0x52>;
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} // isCommutable = 1
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defm LT_S : ComparisonInt<SETLT, "lt_s", 0x48, 0x53>;
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defm LT_U : ComparisonInt<SETULT, "lt_u", 0x49, 0x54>;
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defm GT_S : ComparisonInt<SETGT, "gt_s", 0x4a, 0x55>;
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defm GT_U : ComparisonInt<SETUGT, "gt_u", 0x4b, 0x56>;
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defm LE_S : ComparisonInt<SETLE, "le_s", 0x4c, 0x57>;
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defm LE_U : ComparisonInt<SETULE, "le_u", 0x4d, 0x58>;
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defm GE_S : ComparisonInt<SETGE, "ge_s", 0x4e, 0x59>;
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defm GE_U : ComparisonInt<SETUGE, "ge_u", 0x4f, 0x5a>;
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defm CLZ : UnaryInt<ctlz, "clz ", 0x67, 0x79>;
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defm CTZ : UnaryInt<cttz, "ctz ", 0x68, 0x7a>;
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defm POPCNT : UnaryInt<ctpop, "popcnt", 0x69, 0x7b>;
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defm EQZ_I32 : I<(outs I32:$dst), (ins I32:$src), (outs), (ins),
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[(set I32:$dst, (setcc I32:$src, 0, SETEQ))],
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"i32.eqz \t$dst, $src", "i32.eqz", 0x45>;
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defm EQZ_I64 : I<(outs I32:$dst), (ins I64:$src), (outs), (ins),
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[(set I32:$dst, (setcc I64:$src, 0, SETEQ))],
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"i64.eqz \t$dst, $src", "i64.eqz", 0x50>;
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// Optimize away an explicit mask on a rotate count.
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def : Pat<(rotl I32:$lhs, (and I32:$rhs, 31)), (ROTL_I32 I32:$lhs, I32:$rhs)>;
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def : Pat<(rotr I32:$lhs, (and I32:$rhs, 31)), (ROTR_I32 I32:$lhs, I32:$rhs)>;
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def : Pat<(rotl I64:$lhs, (and I64:$rhs, 63)), (ROTL_I64 I64:$lhs, I64:$rhs)>;
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def : Pat<(rotr I64:$lhs, (and I64:$rhs, 63)), (ROTR_I64 I64:$lhs, I64:$rhs)>;
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defm SELECT_I32 : I<(outs I32:$dst), (ins I32:$lhs, I32:$rhs, I32:$cond),
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(outs), (ins),
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[(set I32:$dst, (select I32:$cond, I32:$lhs, I32:$rhs))],
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"i32.select\t$dst, $lhs, $rhs, $cond", "i32.select", 0x1b>;
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defm SELECT_I64 : I<(outs I64:$dst), (ins I64:$lhs, I64:$rhs, I32:$cond),
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(outs), (ins),
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[(set I64:$dst, (select I32:$cond, I64:$lhs, I64:$rhs))],
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"i64.select\t$dst, $lhs, $rhs, $cond", "i64.select", 0x1b>;
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// ISD::SELECT requires its operand to conform to getBooleanContents, but
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// WebAssembly's select interprets any non-zero value as true, so we can fold
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// a setne with 0 into a select.
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def : Pat<(select (i32 (setne I32:$cond, 0)), I32:$lhs, I32:$rhs),
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(SELECT_I32 I32:$lhs, I32:$rhs, I32:$cond)>;
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def : Pat<(select (i32 (setne I32:$cond, 0)), I64:$lhs, I64:$rhs),
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(SELECT_I64 I64:$lhs, I64:$rhs, I32:$cond)>;
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// And again, this time with seteq instead of setne and the arms reversed.
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def : Pat<(select (i32 (seteq I32:$cond, 0)), I32:$lhs, I32:$rhs),
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(SELECT_I32 I32:$rhs, I32:$lhs, I32:$cond)>;
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def : Pat<(select (i32 (seteq I32:$cond, 0)), I64:$lhs, I64:$rhs),
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(SELECT_I64 I64:$rhs, I64:$lhs, I32:$cond)>;
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