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bbccd10c81
This adds diagnostic strings for the ARM floating-point register classes, which will be used when these classes are expected by the assembler, but the provided operand is not valid. One of these, DPR, requires C++ code to select the correct error message, as that class contains different registers depending on the FPU. The rest can all have their diagnostic strings stored in the tablegen decription of them. Differential revision: https://reviews.llvm.org/D36693 llvm-svn: 315304
27 lines
974 B
ArmAsm
27 lines
974 B
ArmAsm
@ RUN: llvm-mc < %s -triple thumbv7-unknown-unknown -show-encoding -mattr=+vfp4,-d16 2>&1 | FileCheck %s --check-prefix=D32
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@ RUN: not llvm-mc < %s -triple thumbv7-unknown-unknown -show-encoding -mattr=+vfp4,+d16 2>&1 | FileCheck %s --check-prefix=D16
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@ D32-NOT: error:
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@ D16: error: invalid instruction, any one of the following would fix this:
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@ D16-NEXT: vadd.f64 d1, d2, d16
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@ D16: note: operand must be a register in range [d0, d15]
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@ D16: note: too many operands for instruction
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vadd.f64 d1, d2, d16
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@ D16: error: operand must be a register in range [d0, d15]
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@ D16-NEXT: vadd.f64 d1, d17, d6
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vadd.f64 d1, d17, d6
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@ D16: error: operand must be a register in range [d0, d15]
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@ D16-NEXT: vadd.f64 d19, d7, d6
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vadd.f64 d19, d7, d6
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@ D16: error: operand must be a register in range [d0, d15]
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@ D16-NEXT: vcvt.f64.f32 d22, s4
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vcvt.f64.f32 d22, s4
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@ D16: error: operand must be a register in range [d0, d15]
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@ D16-NEXT: vcvt.f32.f64 s26, d30
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vcvt.f32.f64 s26, d30
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