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d09b64fc25
Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT. Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches. Adds a test to verify that the scheduler is working. Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP. Patch by Preston Gurd! llvm-svn: 149558
54 lines
1.9 KiB
LLVM
54 lines
1.9 KiB
LLVM
; RUN: llc < %s -mcpu=generic -march=x86 -mattr=+sse42 -post-RA-scheduler=true | FileCheck %s
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; CHECK: incl
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; CHECK: incl
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; CHECK: incl
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; CHECK: addl
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; Widen a v3i16 to v8i16 to do a vector add
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@.str = internal constant [4 x i8] c"%d \00" ; <[4 x i8]*> [#uses=1]
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@.str1 = internal constant [2 x i8] c"\0A\00" ; <[2 x i8]*> [#uses=1]
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define void @update(<3 x i16>* %dst, <3 x i16>* %src, i32 %n) nounwind {
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entry:
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%dst.addr = alloca <3 x i16>* ; <<3 x i16>**> [#uses=2]
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%src.addr = alloca <3 x i16>* ; <<3 x i16>**> [#uses=2]
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%n.addr = alloca i32 ; <i32*> [#uses=2]
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%v = alloca <3 x i16>, align 8 ; <<3 x i16>*> [#uses=1]
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%i = alloca i32, align 4 ; <i32*> [#uses=6]
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store <3 x i16>* %dst, <3 x i16>** %dst.addr
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store <3 x i16>* %src, <3 x i16>** %src.addr
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store i32 %n, i32* %n.addr
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store <3 x i16> < i16 1, i16 1, i16 1 >, <3 x i16>* %v
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store i32 0, i32* %i
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br label %forcond
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forcond: ; preds = %forinc, %entry
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%tmp = load i32* %i ; <i32> [#uses=1]
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%tmp1 = load i32* %n.addr ; <i32> [#uses=1]
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%cmp = icmp slt i32 %tmp, %tmp1 ; <i1> [#uses=1]
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br i1 %cmp, label %forbody, label %afterfor
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forbody: ; preds = %forcond
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%tmp2 = load i32* %i ; <i32> [#uses=1]
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%tmp3 = load <3 x i16>** %dst.addr ; <<3 x i16>*> [#uses=1]
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%arrayidx = getelementptr <3 x i16>* %tmp3, i32 %tmp2 ; <<3 x i16>*> [#uses=1]
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%tmp4 = load i32* %i ; <i32> [#uses=1]
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%tmp5 = load <3 x i16>** %src.addr ; <<3 x i16>*> [#uses=1]
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%arrayidx6 = getelementptr <3 x i16>* %tmp5, i32 %tmp4 ; <<3 x i16>*> [#uses=1]
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%tmp7 = load <3 x i16>* %arrayidx6 ; <<3 x i16>> [#uses=1]
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%add = add <3 x i16> %tmp7, < i16 1, i16 1, i16 1 > ; <<3 x i16>> [#uses=1]
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store <3 x i16> %add, <3 x i16>* %arrayidx
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br label %forinc
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forinc: ; preds = %forbody
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%tmp8 = load i32* %i ; <i32> [#uses=1]
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%inc = add i32 %tmp8, 1 ; <i32> [#uses=1]
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store i32 %inc, i32* %i
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br label %forcond
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afterfor: ; preds = %forcond
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ret void
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}
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