mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-23 11:13:28 +01:00
02ccf5b7ea
This patch implements the Cortex-A57 scheduling model. The main code is in ARMScheduleA57.td, ARMScheduleA57WriteRes.td. Small changes in cpp,.h files to support required scheduling predicates. Scheduling model implemented according to: http://infocenter.arm.com/help/topic/com.arm.doc.uan0015b/Cortex_A57_Software_Optimization_Guide_external.pdf. Patch by : Andrew Zhogin (submitted on his behalf, as requested). Rewiewed by: Renato Golin, Diana Picus, Javed Absar, Kristof Beyls. Differential Revision: https://reviews.llvm.org/D28152 llvm-svn: 304530
24 lines
694 B
LLVM
24 lines
694 B
LLVM
; REQUIRES: asserts
|
|
; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -misched-postra -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
|
|
|
|
; CHECK: ********** MI Scheduling **********
|
|
; We need second, post-ra scheduling to have VSTM instruction combined from single-stores
|
|
; CHECK: ********** MI Scheduling **********
|
|
; CHECK: schedule starting
|
|
; CHECK: VSTMDIA
|
|
; CHECK: rdefs left
|
|
; CHECK-NEXT: Latency : 2
|
|
|
|
%bigVec = type [2 x double]
|
|
|
|
@var = global %bigVec zeroinitializer
|
|
|
|
define void @bar(%bigVec* %ptr) {
|
|
|
|
%tmp = load %bigVec, %bigVec* %ptr
|
|
store %bigVec %tmp, %bigVec* @var
|
|
|
|
ret void
|
|
}
|
|
|