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The benchmarking summarized in http://lists.llvm.org/pipermail/llvm-dev/2017-May/113525.html showed this is beneficial for a wide range of cores. As is to be expected, quite a few small adaptations are needed to the regressions tests, as the difference in scheduling results in: - Quite a few small instruction schedule differences. - A few changes in register allocation decisions caused by different instruction schedules. - A few changes in IfConversion decisions, due to a difference in instruction schedule and/or the estimated cost of a branch mispredict. llvm-svn: 306514
140 lines
5.9 KiB
LLVM
140 lines
5.9 KiB
LLVM
; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
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define void @vst4i8(i8* %A, <8 x i8>* %B) nounwind {
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;CHECK-LABEL: vst4i8:
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;Check the alignment value. Max for this instruction is 256 bits:
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;CHECK: vst4.8 {d16, d17, d18, d19}, [r0:64]
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%tmp1 = load <8 x i8>, <8 x i8>* %B
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call void @llvm.arm.neon.vst4.p0i8.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 8)
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ret void
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}
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;Check for a post-increment updating store with register increment.
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define void @vst4i8_update(i8** %ptr, <8 x i8>* %B, i32 %inc) nounwind {
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;CHECK-LABEL: vst4i8_update:
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;CHECK: vst4.8 {d16, d17, d18, d19}, [r{{[0-9]+}}:128], r2
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%A = load i8*, i8** %ptr
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%tmp1 = load <8 x i8>, <8 x i8>* %B
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call void @llvm.arm.neon.vst4.p0i8.v8i8(i8* %A, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, <8 x i8> %tmp1, i32 16)
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%tmp2 = getelementptr i8, i8* %A, i32 %inc
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store i8* %tmp2, i8** %ptr
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ret void
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}
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define void @vst4i16(i16* %A, <4 x i16>* %B) nounwind {
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;CHECK-LABEL: vst4i16:
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;Check the alignment value. Max for this instruction is 256 bits:
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;CHECK: vst4.16 {d16, d17, d18, d19}, [r0:128]
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%tmp0 = bitcast i16* %A to i8*
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%tmp1 = load <4 x i16>, <4 x i16>* %B
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call void @llvm.arm.neon.vst4.p0i8.v4i16(i8* %tmp0, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, <4 x i16> %tmp1, i32 16)
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ret void
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}
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define void @vst4i32(i32* %A, <2 x i32>* %B) nounwind {
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;CHECK-LABEL: vst4i32:
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;Check the alignment value. Max for this instruction is 256 bits:
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;CHECK: vst4.32 {d16, d17, d18, d19}, [r0:256]
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%tmp0 = bitcast i32* %A to i8*
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%tmp1 = load <2 x i32>, <2 x i32>* %B
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call void @llvm.arm.neon.vst4.p0i8.v2i32(i8* %tmp0, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, <2 x i32> %tmp1, i32 32)
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ret void
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}
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define void @vst4f(float* %A, <2 x float>* %B) nounwind {
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;CHECK-LABEL: vst4f:
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;CHECK: vst4.32
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%tmp0 = bitcast float* %A to i8*
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%tmp1 = load <2 x float>, <2 x float>* %B
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call void @llvm.arm.neon.vst4.p0i8.v2f32(i8* %tmp0, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, <2 x float> %tmp1, i32 1)
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ret void
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}
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define void @vst4i64(i64* %A, <1 x i64>* %B) nounwind {
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;CHECK-LABEL: vst4i64:
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;Check the alignment value. Max for this instruction is 256 bits:
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;CHECK: vst1.64 {d16, d17, d18, d19}, [r0:256]
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%tmp0 = bitcast i64* %A to i8*
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%tmp1 = load <1 x i64>, <1 x i64>* %B
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call void @llvm.arm.neon.vst4.p0i8.v1i64(i8* %tmp0, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, i32 64)
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ret void
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}
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define void @vst4i64_update(i64** %ptr, <1 x i64>* %B) nounwind {
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;CHECK-LABEL: vst4i64_update:
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;CHECK: vst1.64 {d16, d17, d18, d19}, [r{{[0-9]+}}]!
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%A = load i64*, i64** %ptr
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%tmp0 = bitcast i64* %A to i8*
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%tmp1 = load <1 x i64>, <1 x i64>* %B
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call void @llvm.arm.neon.vst4.p0i8.v1i64(i8* %tmp0, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, <1 x i64> %tmp1, i32 1)
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%tmp2 = getelementptr i64, i64* %A, i32 4
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store i64* %tmp2, i64** %ptr
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ret void
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}
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define void @vst4Qi8(i8* %A, <16 x i8>* %B) nounwind {
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;CHECK-LABEL: vst4Qi8:
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;Check the alignment value. Max for this instruction is 256 bits:
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;CHECK: vst4.8 {d16, d18, d20, d22}, [r0:256]!
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;CHECK: vst4.8 {d17, d19, d21, d23}, [r0:256]
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%tmp1 = load <16 x i8>, <16 x i8>* %B
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call void @llvm.arm.neon.vst4.p0i8.v16i8(i8* %A, <16 x i8> %tmp1, <16 x i8> %tmp1, <16 x i8> %tmp1, <16 x i8> %tmp1, i32 64)
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ret void
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}
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define void @vst4Qi16(i16* %A, <8 x i16>* %B) nounwind {
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;CHECK-LABEL: vst4Qi16:
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;Check for no alignment specifier.
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;CHECK: vst4.16 {d16, d18, d20, d22}, [r0]!
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;CHECK: vst4.16 {d17, d19, d21, d23}, [r0]
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%tmp0 = bitcast i16* %A to i8*
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%tmp1 = load <8 x i16>, <8 x i16>* %B
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call void @llvm.arm.neon.vst4.p0i8.v8i16(i8* %tmp0, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, <8 x i16> %tmp1, i32 1)
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ret void
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}
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define void @vst4Qi32(i32* %A, <4 x i32>* %B) nounwind {
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;CHECK-LABEL: vst4Qi32:
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;CHECK: vst4.32
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;CHECK: vst4.32
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%tmp0 = bitcast i32* %A to i8*
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%tmp1 = load <4 x i32>, <4 x i32>* %B
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call void @llvm.arm.neon.vst4.p0i8.v4i32(i8* %tmp0, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, <4 x i32> %tmp1, i32 1)
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ret void
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}
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define void @vst4Qf(float* %A, <4 x float>* %B) nounwind {
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;CHECK-LABEL: vst4Qf:
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;CHECK: vst4.32
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;CHECK: vst4.32
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%tmp0 = bitcast float* %A to i8*
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%tmp1 = load <4 x float>, <4 x float>* %B
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call void @llvm.arm.neon.vst4.p0i8.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1)
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ret void
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}
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;Check for a post-increment updating store.
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define void @vst4Qf_update(float** %ptr, <4 x float>* %B) nounwind {
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;CHECK-LABEL: vst4Qf_update:
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;CHECK: vst4.32 {d16, d18, d20, d22}, [r[[REG:[0-9]+]]]!
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;CHECK: vst4.32 {d17, d19, d21, d23}, [r[[REG]]]!
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%A = load float*, float** %ptr
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%tmp0 = bitcast float* %A to i8*
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%tmp1 = load <4 x float>, <4 x float>* %B
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call void @llvm.arm.neon.vst4.p0i8.v4f32(i8* %tmp0, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, <4 x float> %tmp1, i32 1)
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%tmp2 = getelementptr float, float* %A, i32 16
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store float* %tmp2, float** %ptr
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ret void
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}
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declare void @llvm.arm.neon.vst4.p0i8.v8i8(i8*, <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8>, i32) nounwind
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declare void @llvm.arm.neon.vst4.p0i8.v4i16(i8*, <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16>, i32) nounwind
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declare void @llvm.arm.neon.vst4.p0i8.v2i32(i8*, <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, i32) nounwind
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declare void @llvm.arm.neon.vst4.p0i8.v2f32(i8*, <2 x float>, <2 x float>, <2 x float>, <2 x float>, i32) nounwind
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declare void @llvm.arm.neon.vst4.p0i8.v1i64(i8*, <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64>, i32) nounwind
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declare void @llvm.arm.neon.vst4.p0i8.v16i8(i8*, <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>, i32) nounwind
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declare void @llvm.arm.neon.vst4.p0i8.v8i16(i8*, <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16>, i32) nounwind
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declare void @llvm.arm.neon.vst4.p0i8.v4i32(i8*, <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32>, i32) nounwind
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declare void @llvm.arm.neon.vst4.p0i8.v4f32(i8*, <4 x float>, <4 x float>, <4 x float>, <4 x float>, i32) nounwind
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