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46 lines
1.2 KiB
LLVM
46 lines
1.2 KiB
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
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; Make sure we don't crash or assert on spir_kernel calling convention.
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; GCN-LABEL: {{^}}kernel:
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; GCN: s_endpgm
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define spir_kernel void @kernel(i32 addrspace(1)* %out) {
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entry:
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store i32 0, i32 addrspace(1)* %out
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ret void
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}
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; FIXME: This is treated like a kernel
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; GCN-LABEL: {{^}}func:
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; GCN: s_endpgm
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define spir_func void @func(i32 addrspace(1)* %out) {
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entry:
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store i32 0, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}ps_ret_cc_f16:
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; SI: v_cvt_f16_f32_e32 v0, v0
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; SI: v_cvt_f32_f16_e32 v0, v0
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; SI: v_add_f32_e32 v0, 1.0, v0
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; VI: v_add_f16_e32 v0, 1.0, v0
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; VI: ; return
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define amdgpu_ps half @ps_ret_cc_f16(half %arg0) {
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%add = fadd half %arg0, 1.0
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ret half %add
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}
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; GCN-LABEL: {{^}}ps_ret_cc_inreg_f16:
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; SI: v_cvt_f16_f32_e32 v0, s0
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; SI: v_cvt_f32_f16_e32 v0, v0
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; SI: v_add_f32_e32 v0, 1.0, v0
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; VI: v_add_f16_e64 v0, s0, 1.0
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; VI: ; return
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define amdgpu_ps half @ps_ret_cc_inreg_f16(half inreg %arg0) {
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%add = fadd half %arg0, 1.0
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ret half %add
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}
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