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81a9bfe915
This switches to the workaround that HSA defaults to for the mesa path. This should be applied to the 4.0 branch. Patch by Vedran Miletić <vedran@miletic.net> llvm-svn: 292982
117 lines
4.3 KiB
LLVM
117 lines
4.3 KiB
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=FUNC %s
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; FIXME: This should be merged with sint_to_fp.ll, but s_sint_to_fp_v2i64 crashes on r600
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; FUNC-LABEL: {{^}}s_sint_to_fp_i64_to_f16:
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define void @s_sint_to_fp_i64_to_f16(half addrspace(1)* %out, i64 %in) #0 {
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%result = sitofp i64 %in to half
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store half %result, half addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}v_sint_to_fp_i64_to_f16:
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; GCN: {{buffer|flat}}_load_dwordx2
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; GCN: v_ashrrev_i32_e32 v{{[0-9]+}}, 31, v{{[0-9]+}}
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; GCN: v_xor_b32
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; GCN: v_ffbh_u32
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; GCN: v_ffbh_u32
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; GCN: v_cndmask
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; GCN: v_cndmask
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; GCN-DAG: v_cmp_eq_u64
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; GCN-DAG: v_cmp_lt_u64
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; GCN: v_xor_b32_e32 v{{[0-9]+}}, 0x80000000, v{{[0-9]+}}
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; GCN: v_cndmask_b32_e{{32|64}} [[SIGN_SEL:v[0-9]+]],
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; GCN: v_cvt_f16_f32_e32 [[SIGN_SEL_F16:v[0-9]+]], [[SIGN_SEL]]
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; GCN: {{buffer|flat}}_store_short {{.*}}[[SIGN_SEL_F16]]
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define void @v_sint_to_fp_i64_to_f16(half addrspace(1)* %out, i64 addrspace(1)* %in) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
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%out.gep = getelementptr half, half addrspace(1)* %out, i32 %tid
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%val = load i64, i64 addrspace(1)* %in.gep
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%result = sitofp i64 %val to half
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store half %result, half addrspace(1)* %out.gep
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ret void
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}
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; FUNC-LABEL: {{^}}s_sint_to_fp_i64_to_f32:
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define void @s_sint_to_fp_i64_to_f32(float addrspace(1)* %out, i64 %in) #0 {
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%result = sitofp i64 %in to float
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store float %result, float addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}v_sint_to_fp_i64_to_f32:
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; GCN: {{buffer|flat}}_load_dwordx2
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; GCN: v_ashrrev_i32_e32 v{{[0-9]+}}, 31, v{{[0-9]+}}
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; GCN: v_xor_b32
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; GCN: v_ffbh_u32
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; GCN: v_ffbh_u32
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; GCN: v_cndmask
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; GCN: v_cndmask
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; GCN-DAG: v_cmp_eq_u64
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; GCN-DAG: v_cmp_lt_u64
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; GCN: v_xor_b32_e32 v{{[0-9]+}}, 0x80000000, v{{[0-9]+}}
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; GCN: v_cndmask_b32_e{{32|64}} [[SIGN_SEL:v[0-9]+]],
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; GCN: {{buffer|flat}}_store_dword {{.*}}[[SIGN_SEL]]
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define void @v_sint_to_fp_i64_to_f32(float addrspace(1)* %out, i64 addrspace(1)* %in) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%in.gep = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
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%out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid
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%val = load i64, i64 addrspace(1)* %in.gep
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%result = sitofp i64 %val to float
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store float %result, float addrspace(1)* %out.gep
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ret void
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}
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; FUNC-LABEL: {{^}}s_sint_to_fp_v2i64_to_v2f32:
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; GCN-NOT: v_and_b32_e32 v{{[0-9]+}}, -1,
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define void @s_sint_to_fp_v2i64_to_v2f32(<2 x float> addrspace(1)* %out, <2 x i64> %in) #0{
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%result = sitofp <2 x i64> %in to <2 x float>
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store <2 x float> %result, <2 x float> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}v_sint_to_fp_v4i64_to_v4f32:
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define void @v_sint_to_fp_v4i64_to_v4f32(<4 x float> addrspace(1)* %out, <4 x i64> addrspace(1)* %in) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%in.gep = getelementptr <4 x i64>, <4 x i64> addrspace(1)* %in, i32 %tid
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%out.gep = getelementptr <4 x float>, <4 x float> addrspace(1)* %out, i32 %tid
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%value = load <4 x i64>, <4 x i64> addrspace(1)* %in.gep
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%result = sitofp <4 x i64> %value to <4 x float>
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store <4 x float> %result, <4 x float> addrspace(1)* %out.gep
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ret void
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}
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; FUNC-LABEL: {{^}}s_sint_to_fp_v2i64_to_v2f16:
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; GCN-NOT: v_and_b32_e32 v{{[0-9]+}}, -1,
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define void @s_sint_to_fp_v2i64_to_v2f16(<2 x half> addrspace(1)* %out, <2 x i64> %in) #0{
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%result = sitofp <2 x i64> %in to <2 x half>
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store <2 x half> %result, <2 x half> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}v_sint_to_fp_v4i64_to_v4f16:
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define void @v_sint_to_fp_v4i64_to_v4f16(<4 x half> addrspace(1)* %out, <4 x i64> addrspace(1)* %in) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%in.gep = getelementptr <4 x i64>, <4 x i64> addrspace(1)* %in, i32 %tid
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%out.gep = getelementptr <4 x half>, <4 x half> addrspace(1)* %out, i32 %tid
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%value = load <4 x i64>, <4 x i64> addrspace(1)* %in.gep
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%result = sitofp <4 x i64> %value to <4 x half>
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store <4 x half> %result, <4 x half> addrspace(1)* %out.gep
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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