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3a9a1ac61b
For some reason there are both of these available, except for scalar 64-bit compares which only has u64. I'm not sure why there are both (I'm guessing it's for the one bit inputs we don't use), but for consistency always using the unsigned one. llvm-svn: 282832
99 lines
3.5 KiB
LLVM
99 lines
3.5 KiB
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s
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declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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; SI-LABEL: {{^}}v_uint_to_fp_i64_to_f64
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; SI: buffer_load_dwordx2 v{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}
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; SI-DAG: v_cvt_f64_u32_e32 [[HI_CONV:v\[[0-9]+:[0-9]+\]]], v[[HI]]
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; SI-DAG: v_cvt_f64_u32_e32 [[LO_CONV:v\[[0-9]+:[0-9]+\]]], v[[LO]]
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; SI-DAG: v_ldexp_f64 [[LDEXP:v\[[0-9]+:[0-9]+\]]], [[HI_CONV]], 32
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; SI: v_add_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[LDEXP]], [[LO_CONV]]
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; SI: buffer_store_dwordx2 [[RESULT]]
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define void @v_uint_to_fp_i64_to_f64(double addrspace(1)* %out, i64 addrspace(1)* %in) {
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%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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%gep = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
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%val = load i64, i64 addrspace(1)* %gep, align 8
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%result = uitofp i64 %val to double
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store double %result, double addrspace(1)* %out
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ret void
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}
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; SI-LABEL: {{^}}s_uint_to_fp_i64_to_f64
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define void @s_uint_to_fp_i64_to_f64(double addrspace(1)* %out, i64 %in) {
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%cast = uitofp i64 %in to double
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store double %cast, double addrspace(1)* %out, align 8
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ret void
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}
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; SI-LABEL: {{^}}s_uint_to_fp_v2i64_to_v2f64
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define void @s_uint_to_fp_v2i64_to_v2f64(<2 x double> addrspace(1)* %out, <2 x i64> %in) {
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%cast = uitofp <2 x i64> %in to <2 x double>
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store <2 x double> %cast, <2 x double> addrspace(1)* %out, align 16
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ret void
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}
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; SI-LABEL: {{^}}s_uint_to_fp_v4i64_to_v4f64
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define void @s_uint_to_fp_v4i64_to_v4f64(<4 x double> addrspace(1)* %out, <4 x i64> %in) {
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%cast = uitofp <4 x i64> %in to <4 x double>
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store <4 x double> %cast, <4 x double> addrspace(1)* %out, align 16
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ret void
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}
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; SI-LABEL: {{^}}s_uint_to_fp_i32_to_f64
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; SI: v_cvt_f64_u32_e32
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; SI: s_endpgm
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define void @s_uint_to_fp_i32_to_f64(double addrspace(1)* %out, i32 %in) {
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%cast = uitofp i32 %in to double
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store double %cast, double addrspace(1)* %out, align 8
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ret void
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}
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; SI-LABEL: {{^}}s_uint_to_fp_v2i32_to_v2f64
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; SI: v_cvt_f64_u32_e32
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; SI: v_cvt_f64_u32_e32
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; SI: s_endpgm
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define void @s_uint_to_fp_v2i32_to_v2f64(<2 x double> addrspace(1)* %out, <2 x i32> %in) {
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%cast = uitofp <2 x i32> %in to <2 x double>
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store <2 x double> %cast, <2 x double> addrspace(1)* %out, align 16
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ret void
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}
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; SI-LABEL: {{^}}s_uint_to_fp_v4i32_to_v4f64
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; SI: v_cvt_f64_u32_e32
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; SI: v_cvt_f64_u32_e32
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; SI: v_cvt_f64_u32_e32
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; SI: v_cvt_f64_u32_e32
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; SI: s_endpgm
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define void @s_uint_to_fp_v4i32_to_v4f64(<4 x double> addrspace(1)* %out, <4 x i32> %in) {
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%cast = uitofp <4 x i32> %in to <4 x double>
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store <4 x double> %cast, <4 x double> addrspace(1)* %out, align 16
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ret void
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}
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; We can't fold the SGPRs into v_cndmask_b32_e32, because it already
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; uses an SGPR (implicit vcc).
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; SI-LABEL: {{^}}uint_to_fp_i1_to_f64:
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; SI-DAG: v_cmp_eq_u32_e64 vcc
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; SI-DAG: v_cndmask_b32_e32 v[[SEL:[0-9]+]], 0, v{{[0-9]+}}
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; SI-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}}
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; SI: buffer_store_dwordx2 v{{\[}}[[ZERO]]:[[SEL]]{{\]}}
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; SI: s_endpgm
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define void @uint_to_fp_i1_to_f64(double addrspace(1)* %out, i32 %in) {
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%cmp = icmp eq i32 %in, 0
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%fp = uitofp i1 %cmp to double
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store double %fp, double addrspace(1)* %out, align 4
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ret void
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}
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; SI-LABEL: {{^}}uint_to_fp_i1_to_f64_load:
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; SI: v_cndmask_b32_e64 [[IRESULT:v[0-9]]], 0, 1
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; SI-NEXT: v_cvt_f64_u32_e32 [[RESULT:v\[[0-9]+:[0-9]\]]], [[IRESULT]]
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; SI: buffer_store_dwordx2 [[RESULT]]
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; SI: s_endpgm
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define void @uint_to_fp_i1_to_f64_load(double addrspace(1)* %out, i1 %in) {
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%fp = uitofp i1 %in to double
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store double %fp, double addrspace(1)* %out, align 8
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ret void
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}
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