Bruno Cardoso Lopes f29783ee55 We already support 256-bit packed ADD, SUB, DIV, MUL. Add testcases. ... llvm-svn: 135099		2011-07-13 22:28:55 +00:00
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Alpha
ARM	Improve codegen for select's:	2011-07-13 00:42:17 +00:00
Blackfin	more tests not making the jump into the brave new world.	2011-07-09 16:57:10 +00:00
CBackend	more tests not making the jump into the brave new world.	2011-07-09 16:57:10 +00:00
CellSPU
CPP
Generic	Comment correction.	2011-07-12 03:39:22 +00:00
MBlaze
Mips
MSP430
PowerPC	test/CodeGen/PowerPC/vector.ll: Tweak redirection >%t >%t to >%t >>%t. See also r134814 (test/CodeGen/X86/vector.ll).	2011-07-11 16:21:52 +00:00
PTX
SPARC
SystemZ
Thumb	Change some ARM subtarget features to be single bit yes/no in order to sink them down to MC layer. Also fix tests.	2011-07-07 03:55:05 +00:00
Thumb2	Improve codegen for select's:	2011-07-13 00:42:17 +00:00
X86	We already support 256-bit packed ADD, SUB, DIV, MUL. Add testcases.	2011-07-13 22:28:55 +00:00
XCore