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339 lines
10 KiB
C++
339 lines
10 KiB
C++
//===-- AArch64CondBrTuning.cpp --- Conditional branch tuning for AArch64 -===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file contains a pass that transforms CBZ/CBNZ/TBZ/TBNZ instructions
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/// into a conditional branch (B.cond), when the NZCV flags can be set for
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/// "free". This is preferred on targets that have more flexibility when
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/// scheduling B.cond instructions as compared to CBZ/CBNZ/TBZ/TBNZ (assuming
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/// all other variables are equal). This can also reduce register pressure.
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///
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/// A few examples:
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///
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/// 1) add w8, w0, w1 -> cmn w0, w1 ; CMN is an alias of ADDS.
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/// cbz w8, .LBB_2 -> b.eq .LBB0_2
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///
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/// 2) add w8, w0, w1 -> adds w8, w0, w1 ; w8 has multiple uses.
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/// cbz w8, .LBB1_2 -> b.eq .LBB1_2
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///
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/// 3) sub w8, w0, w1 -> subs w8, w0, w1 ; w8 has multiple uses.
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/// tbz w8, #31, .LBB6_2 -> b.pl .LBB6_2
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///
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//===----------------------------------------------------------------------===//
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#include "AArch64.h"
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#include "AArch64Subtarget.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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#define DEBUG_TYPE "aarch64-cond-br-tuning"
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#define AARCH64_CONDBR_TUNING_NAME "AArch64 Conditional Branch Tuning"
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namespace {
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class AArch64CondBrTuning : public MachineFunctionPass {
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const AArch64InstrInfo *TII;
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const TargetRegisterInfo *TRI;
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MachineRegisterInfo *MRI;
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public:
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static char ID;
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AArch64CondBrTuning() : MachineFunctionPass(ID) {
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initializeAArch64CondBrTuningPass(*PassRegistry::getPassRegistry());
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override;
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bool runOnMachineFunction(MachineFunction &MF) override;
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StringRef getPassName() const override { return AARCH64_CONDBR_TUNING_NAME; }
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private:
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MachineInstr *getOperandDef(const MachineOperand &MO);
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MachineInstr *convertToFlagSetting(MachineInstr &MI, bool IsFlagSetting);
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MachineInstr *convertToCondBr(MachineInstr &MI);
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bool tryToTuneBranch(MachineInstr &MI, MachineInstr &DefMI);
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};
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} // end anonymous namespace
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char AArch64CondBrTuning::ID = 0;
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INITIALIZE_PASS(AArch64CondBrTuning, "aarch64-cond-br-tuning",
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AARCH64_CONDBR_TUNING_NAME, false, false)
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void AArch64CondBrTuning::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesCFG();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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MachineInstr *AArch64CondBrTuning::getOperandDef(const MachineOperand &MO) {
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if (!TargetRegisterInfo::isVirtualRegister(MO.getReg()))
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return nullptr;
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return MRI->getUniqueVRegDef(MO.getReg());
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}
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MachineInstr *AArch64CondBrTuning::convertToFlagSetting(MachineInstr &MI,
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bool IsFlagSetting) {
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// If this is already the flag setting version of the instruction (e.g., SUBS)
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// just make sure the implicit-def of NZCV isn't marked dead.
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if (IsFlagSetting) {
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for (unsigned I = MI.getNumExplicitOperands(), E = MI.getNumOperands();
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I != E; ++I) {
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MachineOperand &MO = MI.getOperand(I);
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if (MO.isReg() && MO.isDead() && MO.getReg() == AArch64::NZCV)
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MO.setIsDead(false);
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}
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return &MI;
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}
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bool Is64Bit;
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unsigned NewOpc = TII->convertToFlagSettingOpc(MI.getOpcode(), Is64Bit);
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unsigned NewDestReg = MI.getOperand(0).getReg();
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if (MRI->hasOneNonDBGUse(MI.getOperand(0).getReg()))
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NewDestReg = Is64Bit ? AArch64::XZR : AArch64::WZR;
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MachineInstrBuilder MIB = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(),
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TII->get(NewOpc), NewDestReg);
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for (unsigned I = 1, E = MI.getNumOperands(); I != E; ++I)
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MIB.add(MI.getOperand(I));
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return MIB;
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}
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MachineInstr *AArch64CondBrTuning::convertToCondBr(MachineInstr &MI) {
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AArch64CC::CondCode CC;
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MachineBasicBlock *TargetMBB = TII->getBranchDestBlock(MI);
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switch (MI.getOpcode()) {
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default:
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llvm_unreachable("Unexpected opcode!");
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case AArch64::CBZW:
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case AArch64::CBZX:
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CC = AArch64CC::EQ;
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break;
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case AArch64::CBNZW:
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case AArch64::CBNZX:
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CC = AArch64CC::NE;
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break;
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case AArch64::TBZW:
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case AArch64::TBZX:
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CC = AArch64CC::PL;
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break;
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case AArch64::TBNZW:
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case AArch64::TBNZX:
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CC = AArch64CC::MI;
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break;
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}
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return BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), TII->get(AArch64::Bcc))
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.addImm(CC)
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.addMBB(TargetMBB);
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}
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bool AArch64CondBrTuning::tryToTuneBranch(MachineInstr &MI,
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MachineInstr &DefMI) {
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// We don't want NZCV bits live across blocks.
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if (MI.getParent() != DefMI.getParent())
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return false;
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bool IsFlagSetting = true;
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unsigned MIOpc = MI.getOpcode();
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MachineInstr *NewCmp = nullptr, *NewBr = nullptr;
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switch (DefMI.getOpcode()) {
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default:
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return false;
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case AArch64::ADDWri:
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case AArch64::ADDWrr:
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case AArch64::ADDWrs:
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case AArch64::ADDWrx:
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case AArch64::ANDWri:
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case AArch64::ANDWrr:
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case AArch64::ANDWrs:
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case AArch64::BICWrr:
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case AArch64::BICWrs:
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case AArch64::SUBWri:
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case AArch64::SUBWrr:
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case AArch64::SUBWrs:
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case AArch64::SUBWrx:
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IsFlagSetting = false;
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LLVM_FALLTHROUGH;
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case AArch64::ADDSWri:
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case AArch64::ADDSWrr:
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case AArch64::ADDSWrs:
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case AArch64::ADDSWrx:
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case AArch64::ANDSWri:
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case AArch64::ANDSWrr:
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case AArch64::ANDSWrs:
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case AArch64::BICSWrr:
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case AArch64::BICSWrs:
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case AArch64::SUBSWri:
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case AArch64::SUBSWrr:
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case AArch64::SUBSWrs:
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case AArch64::SUBSWrx:
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switch (MIOpc) {
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default:
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llvm_unreachable("Unexpected opcode!");
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case AArch64::CBZW:
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case AArch64::CBNZW:
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case AArch64::TBZW:
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case AArch64::TBNZW:
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// Check to see if the TBZ/TBNZ is checking the sign bit.
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if ((MIOpc == AArch64::TBZW || MIOpc == AArch64::TBNZW) &&
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MI.getOperand(1).getImm() != 31)
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return false;
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// There must not be any instruction between DefMI and MI that clobbers or
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// reads NZCV.
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MachineBasicBlock::iterator I(DefMI), E(MI);
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for (I = std::next(I); I != E; ++I) {
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if (I->modifiesRegister(AArch64::NZCV, TRI) ||
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I->readsRegister(AArch64::NZCV, TRI))
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return false;
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}
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LLVM_DEBUG(dbgs() << " Replacing instructions:\n ");
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LLVM_DEBUG(DefMI.print(dbgs()));
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LLVM_DEBUG(dbgs() << " ");
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LLVM_DEBUG(MI.print(dbgs()));
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NewCmp = convertToFlagSetting(DefMI, IsFlagSetting);
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NewBr = convertToCondBr(MI);
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break;
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}
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break;
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case AArch64::ADDXri:
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case AArch64::ADDXrr:
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case AArch64::ADDXrs:
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case AArch64::ADDXrx:
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case AArch64::ANDXri:
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case AArch64::ANDXrr:
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case AArch64::ANDXrs:
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case AArch64::BICXrr:
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case AArch64::BICXrs:
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case AArch64::SUBXri:
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case AArch64::SUBXrr:
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case AArch64::SUBXrs:
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case AArch64::SUBXrx:
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IsFlagSetting = false;
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LLVM_FALLTHROUGH;
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case AArch64::ADDSXri:
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case AArch64::ADDSXrr:
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case AArch64::ADDSXrs:
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case AArch64::ADDSXrx:
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case AArch64::ANDSXri:
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case AArch64::ANDSXrr:
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case AArch64::ANDSXrs:
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case AArch64::BICSXrr:
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case AArch64::BICSXrs:
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case AArch64::SUBSXri:
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case AArch64::SUBSXrr:
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case AArch64::SUBSXrs:
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case AArch64::SUBSXrx:
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switch (MIOpc) {
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default:
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llvm_unreachable("Unexpected opcode!");
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case AArch64::CBZX:
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case AArch64::CBNZX:
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case AArch64::TBZX:
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case AArch64::TBNZX: {
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// Check to see if the TBZ/TBNZ is checking the sign bit.
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if ((MIOpc == AArch64::TBZX || MIOpc == AArch64::TBNZX) &&
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MI.getOperand(1).getImm() != 63)
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return false;
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// There must not be any instruction between DefMI and MI that clobbers or
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// reads NZCV.
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MachineBasicBlock::iterator I(DefMI), E(MI);
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for (I = std::next(I); I != E; ++I) {
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if (I->modifiesRegister(AArch64::NZCV, TRI) ||
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I->readsRegister(AArch64::NZCV, TRI))
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return false;
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}
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LLVM_DEBUG(dbgs() << " Replacing instructions:\n ");
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LLVM_DEBUG(DefMI.print(dbgs()));
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LLVM_DEBUG(dbgs() << " ");
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LLVM_DEBUG(MI.print(dbgs()));
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NewCmp = convertToFlagSetting(DefMI, IsFlagSetting);
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NewBr = convertToCondBr(MI);
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break;
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}
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}
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break;
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}
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(void)NewCmp; (void)NewBr;
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assert(NewCmp && NewBr && "Expected new instructions.");
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LLVM_DEBUG(dbgs() << " with instruction:\n ");
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LLVM_DEBUG(NewCmp->print(dbgs()));
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LLVM_DEBUG(dbgs() << " ");
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LLVM_DEBUG(NewBr->print(dbgs()));
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// If this was a flag setting version of the instruction, we use the original
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// instruction by just clearing the dead marked on the implicit-def of NCZV.
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// Therefore, we should not erase this instruction.
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if (!IsFlagSetting)
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DefMI.eraseFromParent();
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MI.eraseFromParent();
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return true;
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}
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bool AArch64CondBrTuning::runOnMachineFunction(MachineFunction &MF) {
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if (skipFunction(MF.getFunction()))
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return false;
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LLVM_DEBUG(
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dbgs() << "********** AArch64 Conditional Branch Tuning **********\n"
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<< "********** Function: " << MF.getName() << '\n');
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TII = static_cast<const AArch64InstrInfo *>(MF.getSubtarget().getInstrInfo());
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TRI = MF.getSubtarget().getRegisterInfo();
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MRI = &MF.getRegInfo();
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bool Changed = false;
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for (MachineBasicBlock &MBB : MF) {
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bool LocalChange = false;
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for (MachineBasicBlock::iterator I = MBB.getFirstTerminator(),
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E = MBB.end();
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I != E; ++I) {
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MachineInstr &MI = *I;
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switch (MI.getOpcode()) {
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default:
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break;
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case AArch64::CBZW:
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case AArch64::CBZX:
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case AArch64::CBNZW:
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case AArch64::CBNZX:
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case AArch64::TBZW:
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case AArch64::TBZX:
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case AArch64::TBNZW:
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case AArch64::TBNZX:
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MachineInstr *DefMI = getOperandDef(MI.getOperand(0));
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LocalChange = (DefMI && tryToTuneBranch(MI, *DefMI));
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break;
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}
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// If the optimization was successful, we can't optimize any other
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// branches because doing so would clobber the NZCV flags.
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if (LocalChange) {
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Changed = true;
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break;
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}
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}
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}
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return Changed;
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}
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FunctionPass *llvm::createAArch64CondBrTuning() {
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return new AArch64CondBrTuning();
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}
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