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de0bb2f505
This is the result of discussions on the list about how to deal with intrinsics which require codegen to disambiguate them via only the integer/fp overloads. It causes problems for GlobalISel as some of that information is lost during translation, while with other operations like IR instructions the information is encoded into the instruction opcode. This patch changes clang to emit the new faddp intrinsic if the vector operands to the builtin have FP element types. LLVM IR AutoUpgrade has been taught to upgrade existing calls to aarch64.neon.addp with fp vector arguments, and we remove the workarounds introduced for GlobalISel in r355865. This is a more permanent solution to PR40968. Differential Revision: https://reviews.llvm.org/D59655 llvm-svn: 356722
40 lines
1.4 KiB
C++
40 lines
1.4 KiB
C++
//===- AArch64LegalizerInfo --------------------------------------*- C++ -*-==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file declares the targeting of the Machinelegalizer class for
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/// AArch64.
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/// \todo This should be generated by TableGen.
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64MACHINELEGALIZER_H
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#define LLVM_LIB_TARGET_AARCH64_AARCH64MACHINELEGALIZER_H
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#include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h"
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#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
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namespace llvm {
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class LLVMContext;
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class AArch64Subtarget;
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/// This class provides the information for the target register banks.
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class AArch64LegalizerInfo : public LegalizerInfo {
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public:
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AArch64LegalizerInfo(const AArch64Subtarget &ST);
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bool legalizeCustom(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &MIRBuilder,
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GISelChangeObserver &Observer) const override;
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private:
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bool legalizeVaArg(MachineInstr &MI, MachineRegisterInfo &MRI,
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MachineIRBuilder &MIRBuilder) const;
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};
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} // End llvm namespace.
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#endif
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