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370 lines
10 KiB
C++
370 lines
10 KiB
C++
//===-- AMDGPUSubtarget.cpp - AMDGPU Subtarget Information ----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// \brief Implements the AMDGPU specific subclass of TargetSubtarget.
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPUSubtarget.h"
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#include "R600ISelLowering.h"
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#include "R600InstrInfo.h"
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#include "SIFrameLowering.h"
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#include "SIISelLowering.h"
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#include "SIInstrInfo.h"
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#include "SIMachineFunctionInfo.h"
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#include "llvm/ADT/SmallString.h"
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#include "llvm/CodeGen/MachineScheduler.h"
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using namespace llvm;
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#define DEBUG_TYPE "amdgpu-subtarget"
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#define GET_SUBTARGETINFO_ENUM
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#define GET_SUBTARGETINFO_TARGET_DESC
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#define GET_SUBTARGETINFO_CTOR
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#include "AMDGPUGenSubtargetInfo.inc"
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AMDGPUSubtarget::~AMDGPUSubtarget() {}
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AMDGPUSubtarget &
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AMDGPUSubtarget::initializeSubtargetDependencies(const Triple &TT,
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StringRef GPU, StringRef FS) {
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// Determine default and user-specified characteristics
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// On SI+, we want FP64 denormals to be on by default. FP32 denormals can be
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// enabled, but some instructions do not respect them and they run at the
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// double precision rate, so don't enable by default.
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//
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// We want to be able to turn these off, but making this a subtarget feature
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// for SI has the unhelpful behavior that it unsets everything else if you
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// disable it.
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SmallString<256> FullFS("+promote-alloca,+fp64-denormals,+load-store-opt,");
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if (isAmdHsaOS()) // Turn on FlatForGlobal for HSA.
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FullFS += "+flat-for-global,+unaligned-buffer-access,";
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FullFS += FS;
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ParseSubtargetFeatures(GPU, FullFS);
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// FIXME: I don't think think Evergreen has any useful support for
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// denormals, but should be checked. Should we issue a warning somewhere
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// if someone tries to enable these?
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if (getGeneration() <= AMDGPUSubtarget::NORTHERN_ISLANDS) {
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FP16Denormals = false;
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FP32Denormals = false;
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FP64Denormals = false;
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}
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// Set defaults if needed.
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if (MaxPrivateElementSize == 0)
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MaxPrivateElementSize = 4;
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return *this;
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}
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AMDGPUSubtarget::AMDGPUSubtarget(const Triple &TT, StringRef GPU, StringRef FS,
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const TargetMachine &TM)
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: AMDGPUGenSubtargetInfo(TT, GPU, FS),
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TargetTriple(TT),
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Gen(TT.getArch() == Triple::amdgcn ? SOUTHERN_ISLANDS : R600),
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IsaVersion(ISAVersion0_0_0),
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WavefrontSize(64),
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LocalMemorySize(0),
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LDSBankCount(0),
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MaxPrivateElementSize(0),
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FastFMAF32(false),
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HalfRate64Ops(false),
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FP16Denormals(false),
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FP32Denormals(false),
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FP64Denormals(false),
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FPExceptions(false),
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FlatForGlobal(false),
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UnalignedScratchAccess(false),
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UnalignedBufferAccess(false),
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EnableXNACK(false),
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DebuggerInsertNops(false),
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DebuggerReserveRegs(false),
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DebuggerEmitPrologue(false),
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EnableVGPRSpilling(false),
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EnablePromoteAlloca(false),
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EnableLoadStoreOpt(false),
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EnableUnsafeDSOffsetFolding(false),
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EnableSIScheduler(false),
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DumpCode(false),
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FP64(false),
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IsGCN(false),
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GCN1Encoding(false),
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GCN3Encoding(false),
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CIInsts(false),
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SGPRInitBug(false),
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HasSMemRealTime(false),
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Has16BitInsts(false),
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HasMovrel(false),
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HasVGPRIndexMode(false),
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HasScalarStores(false),
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HasInv2PiInlineImm(false),
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FlatAddressSpace(false),
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R600ALUInst(false),
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CaymanISA(false),
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CFALUBug(false),
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HasVertexCache(false),
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TexVTXClauseSize(0),
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FeatureDisable(false),
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InstrItins(getInstrItineraryForCPU(GPU)),
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TSInfo() {
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initializeSubtargetDependencies(TT, GPU, FS);
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}
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// FIXME: These limits are for SI. Did they change with the larger maximum LDS
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// size?
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unsigned AMDGPUSubtarget::getMaxLocalMemSizeWithWaveCount(unsigned NWaves) const {
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switch (NWaves) {
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case 10:
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return 1638;
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case 9:
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return 1820;
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case 8:
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return 2048;
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case 7:
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return 2340;
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case 6:
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return 2730;
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case 5:
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return 3276;
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case 4:
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return 4096;
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case 3:
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return 5461;
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case 2:
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return 8192;
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default:
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return getLocalMemorySize();
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}
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}
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unsigned AMDGPUSubtarget::getOccupancyWithLocalMemSize(uint32_t Bytes) const {
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if (Bytes <= 1638)
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return 10;
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if (Bytes <= 1820)
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return 9;
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if (Bytes <= 2048)
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return 8;
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if (Bytes <= 2340)
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return 7;
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if (Bytes <= 2730)
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return 6;
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if (Bytes <= 3276)
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return 5;
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if (Bytes <= 4096)
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return 4;
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if (Bytes <= 5461)
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return 3;
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if (Bytes <= 8192)
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return 2;
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return 1;
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}
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std::pair<unsigned, unsigned> AMDGPUSubtarget::getFlatWorkGroupSizes(
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const Function &F) const {
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// Default minimum/maximum flat work group sizes.
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std::pair<unsigned, unsigned> Default =
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AMDGPU::isCompute(F.getCallingConv()) ?
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std::pair<unsigned, unsigned>(getWavefrontSize() * 2,
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getWavefrontSize() * 4) :
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std::pair<unsigned, unsigned>(1, getWavefrontSize());
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// TODO: Do not process "amdgpu-max-work-group-size" attribute once mesa
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// starts using "amdgpu-flat-work-group-size" attribute.
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Default.second = AMDGPU::getIntegerAttribute(
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F, "amdgpu-max-work-group-size", Default.second);
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Default.first = std::min(Default.first, Default.second);
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// Requested minimum/maximum flat work group sizes.
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std::pair<unsigned, unsigned> Requested = AMDGPU::getIntegerPairAttribute(
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F, "amdgpu-flat-work-group-size", Default);
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// Make sure requested minimum is less than requested maximum.
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if (Requested.first > Requested.second)
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return Default;
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// Make sure requested values do not violate subtarget's specifications.
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if (Requested.first < getMinFlatWorkGroupSize())
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return Default;
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if (Requested.second > getMaxFlatWorkGroupSize())
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return Default;
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return Requested;
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}
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std::pair<unsigned, unsigned> AMDGPUSubtarget::getWavesPerEU(
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const Function &F) const {
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// Default minimum/maximum number of waves per execution unit.
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std::pair<unsigned, unsigned> Default(1, 0);
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// Default/requested minimum/maximum flat work group sizes.
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std::pair<unsigned, unsigned> FlatWorkGroupSizes = getFlatWorkGroupSizes(F);
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// If minimum/maximum flat work group sizes were explicitly requested using
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// "amdgpu-flat-work-group-size" attribute, then set default minimum/maximum
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// number of waves per execution unit to values implied by requested
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// minimum/maximum flat work group sizes.
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unsigned MinImpliedByFlatWorkGroupSize =
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getMaxWavesPerEU(FlatWorkGroupSizes.second);
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bool RequestedFlatWorkGroupSize = false;
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// TODO: Do not process "amdgpu-max-work-group-size" attribute once mesa
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// starts using "amdgpu-flat-work-group-size" attribute.
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if (F.hasFnAttribute("amdgpu-max-work-group-size") ||
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F.hasFnAttribute("amdgpu-flat-work-group-size")) {
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Default.first = MinImpliedByFlatWorkGroupSize;
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RequestedFlatWorkGroupSize = true;
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}
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// Requested minimum/maximum number of waves per execution unit.
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std::pair<unsigned, unsigned> Requested = AMDGPU::getIntegerPairAttribute(
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F, "amdgpu-waves-per-eu", Default, true);
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// Make sure requested minimum is less than requested maximum.
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if (Requested.second && Requested.first > Requested.second)
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return Default;
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// Make sure requested values do not violate subtarget's specifications.
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if (Requested.first < getMinWavesPerEU() ||
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Requested.first > getMaxWavesPerEU())
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return Default;
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if (Requested.second > getMaxWavesPerEU())
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return Default;
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// Make sure requested values are compatible with values implied by requested
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// minimum/maximum flat work group sizes.
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if (RequestedFlatWorkGroupSize &&
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Requested.first > MinImpliedByFlatWorkGroupSize)
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return Default;
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return Requested;
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}
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R600Subtarget::R600Subtarget(const Triple &TT, StringRef GPU, StringRef FS,
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const TargetMachine &TM) :
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AMDGPUSubtarget(TT, GPU, FS, TM),
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InstrInfo(*this),
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FrameLowering(TargetFrameLowering::StackGrowsUp, getStackAlignment(), 0),
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TLInfo(TM, *this) {}
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SISubtarget::SISubtarget(const Triple &TT, StringRef GPU, StringRef FS,
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const TargetMachine &TM) :
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AMDGPUSubtarget(TT, GPU, FS, TM),
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InstrInfo(*this),
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FrameLowering(TargetFrameLowering::StackGrowsUp, getStackAlignment(), 0),
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TLInfo(TM, *this),
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GISel() {}
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void SISubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
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unsigned NumRegionInstrs) const {
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// Track register pressure so the scheduler can try to decrease
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// pressure once register usage is above the threshold defined by
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// SIRegisterInfo::getRegPressureSetLimit()
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Policy.ShouldTrackPressure = true;
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// Enabling both top down and bottom up scheduling seems to give us less
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// register spills than just using one of these approaches on its own.
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Policy.OnlyTopDown = false;
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Policy.OnlyBottomUp = false;
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// Enabling ShouldTrackLaneMasks crashes the SI Machine Scheduler.
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if (!enableSIScheduler())
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Policy.ShouldTrackLaneMasks = true;
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}
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bool SISubtarget::isVGPRSpillingEnabled(const Function& F) const {
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return EnableVGPRSpilling || !AMDGPU::isShader(F.getCallingConv());
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}
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unsigned SISubtarget::getKernArgSegmentSize(unsigned ExplicitArgBytes) const {
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unsigned ImplicitBytes = getImplicitArgNumBytes();
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if (ImplicitBytes == 0)
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return ExplicitArgBytes;
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unsigned Alignment = getAlignmentForImplicitArgPtr();
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return alignTo(ExplicitArgBytes, Alignment) + ImplicitBytes;
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}
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unsigned SISubtarget::getOccupancyWithNumSGPRs(unsigned SGPRs) const {
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if (getGeneration() >= SISubtarget::VOLCANIC_ISLANDS) {
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if (SGPRs <= 80)
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return 10;
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if (SGPRs <= 88)
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return 9;
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if (SGPRs <= 100)
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return 8;
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return 7;
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}
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if (SGPRs <= 48)
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return 10;
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if (SGPRs <= 56)
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return 9;
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if (SGPRs <= 64)
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return 8;
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if (SGPRs <= 72)
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return 7;
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if (SGPRs <= 80)
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return 6;
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return 5;
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}
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unsigned SISubtarget::getOccupancyWithNumVGPRs(unsigned VGPRs) const {
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if (VGPRs <= 24)
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return 10;
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if (VGPRs <= 28)
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return 9;
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if (VGPRs <= 32)
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return 8;
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if (VGPRs <= 36)
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return 7;
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if (VGPRs <= 40)
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return 6;
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if (VGPRs <= 48)
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return 5;
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if (VGPRs <= 64)
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return 4;
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if (VGPRs <= 84)
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return 3;
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if (VGPRs <= 128)
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return 2;
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return 1;
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}
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unsigned SISubtarget::getMaxNumSGPRs() const {
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if (hasSGPRInitBug())
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return SISubtarget::FIXED_SGPR_COUNT_FOR_INIT_BUG;
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if (getGeneration() >= VOLCANIC_ISLANDS)
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return 102;
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return 104;
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}
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