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2567a1faf7
%lo(), %hi(), and %pcrel_hi() are supported and test cases have been added to ensure the appropriate fixups and relocations are generated. I've added an instruction format field which is used in RISCVMCCodeEmitter to, for instance, tell whether it should emit a lo12_i fixup or a lo12_s fixup (RISC-V has two 12-bit immediate encodings depending on the instruction type). Differential Revision: https://reviews.llvm.org/D23568 llvm-svn: 314389
40 lines
1.2 KiB
ArmAsm
40 lines
1.2 KiB
ArmAsm
# RUN: llvm-mc -filetype=obj -triple=riscv32 %s \
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# RUN: | llvm-objdump -d - | FileCheck %s -check-prefix=CHECK-INSTR
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# RUN: llvm-mc -filetype=obj -triple=riscv32 %s \
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# RUN: | llvm-readobj -r | FileCheck %s -check-prefix=CHECK-REL
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# Check the assembler can handle hi and lo expressions with a constant
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# address, and constant expressions involving labels. Test case derived from
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# test/MC/Mips/hilo-addressing.s
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# Check that 1 is added to the high 20 bits if bit 11 of the low part is 1.
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.equ addr, 0xdeadbeef
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lui t0, %hi(addr)
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lw ra, %lo(addr)(t0)
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# CHECK-INSTR: lui t0, 912092
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# CHECK-INSTR: lw ra, -273(t0)
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# Check that assembler can handle %hi(label1 - label2) and %lo(label1 - label2)
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# expressions.
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tmp1:
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# Emit zeros so that difference between tmp1 and tmp3 is 0x30124 bytes.
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.fill 0x30124-8
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tmp2:
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lui t0, %hi(tmp3-tmp1)
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lw ra, %lo(tmp3-tmp1)(t0)
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# CHECK-INSTR: lui t0, 48
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# CHECK-INSTR: lw ra, 292(t0)
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tmp3:
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lui t1, %hi(tmp2-tmp3)
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lw sp, %lo(tmp2-tmp3)(t1)
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# CHECK-INSTR: lui t1, 0
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# CHECK-INSTR: lw sp, -8(t1)
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# Check that a relocation isn't emitted for %hi(label1 - label2) and
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# %lo(label1 - label2) expressions.
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# CHECK-REL-NOT: R_RISCV
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