mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-31 16:02:52 +01:00
127 lines
5.2 KiB
ArmAsm
127 lines
5.2 KiB
ArmAsm
@ RUN: llvm-mc -triple=thumbv7-apple-darwin -show-encoding < %s | FileCheck %s
|
|
.syntax unified
|
|
.globl _func
|
|
|
|
@ Check that the assembler can handle the documented syntax from the ARM ARM.
|
|
@ For complex constructs like shifter operands, check more thoroughly for them
|
|
@ once then spot check that following instructions accept the form generally.
|
|
@ This gives us good coverage while keeping the overall size of the test
|
|
@ more reasonable.
|
|
|
|
|
|
@ FIXME: Some 3-operand instructions have a 2-operand assembly syntax.
|
|
|
|
_func:
|
|
@ CHECK: _func
|
|
|
|
@------------------------------------------------------------------------------
|
|
@ ADC (immediate)
|
|
@------------------------------------------------------------------------------
|
|
adc r0, r1, #4
|
|
adcs r0, r1, #0
|
|
adc r1, r2, #255
|
|
adc r3, r7, #0x00550055
|
|
adc r8, r12, #0xaa00aa00
|
|
adc r9, r7, #0xa5a5a5a5
|
|
adc r5, r3, #0x87000000
|
|
adc r4, r2, #0x7f800000
|
|
adc r4, r2, #0x00000680
|
|
|
|
@ CHECK: adc r0, r1, #4 @ encoding: [0x41,0xf1,0x04,0x00]
|
|
@ CHECK: adcs r0, r1, #0 @ encoding: [0x51,0xf1,0x00,0x00]
|
|
@ CHECK: adc r1, r2, #255 @ encoding: [0x42,0xf1,0xff,0x01]
|
|
@ CHECK: adc r3, r7, #5570645 @ encoding: [0x47,0xf1,0x55,0x13]
|
|
@ CHECK: adc r8, r12, #2852170240 @ encoding: [0x4c,0xf1,0xaa,0x28]
|
|
@ CHECK: adc r9, r7, #2779096485 @ encoding: [0x47,0xf1,0xa5,0x39]
|
|
@ CHECK: adc r5, r3, #2264924160 @ encoding: [0x43,0xf1,0x07,0x45]
|
|
@ CHECK: adc r4, r2, #2139095040 @ encoding: [0x42,0xf1,0xff,0x44]
|
|
@ CHECK: adc r4, r2, #1664 @ encoding: [0x42,0xf5,0xd0,0x64]
|
|
|
|
@------------------------------------------------------------------------------
|
|
@ ADC (register)
|
|
@------------------------------------------------------------------------------
|
|
adc r4, r5, r6
|
|
adcs r4, r5, r6
|
|
adc.w r9, r1, r3
|
|
adcs.w r9, r1, r3
|
|
adc r0, r1, r3, ror #4
|
|
adcs r0, r1, r3, lsl #7
|
|
adc.w r0, r1, r3, lsr #31
|
|
adcs.w r0, r1, r3, asr #32
|
|
|
|
@ CHECK: adc.w r4, r5, r6 @ encoding: [0x45,0xeb,0x06,0x04]
|
|
@ CHECK: adcs.w r4, r5, r6 @ encoding: [0x55,0xeb,0x06,0x04]
|
|
@ CHECK: adc.w r9, r1, r3 @ encoding: [0x41,0xeb,0x03,0x09]
|
|
@ CHECK: adcs.w r9, r1, r3 @ encoding: [0x51,0xeb,0x03,0x09]
|
|
@ CHECK: adc.w r0, r1, r3, ror #4 @ encoding: [0x41,0xeb,0x33,0x10]
|
|
@ CHECK: adcs.w r0, r1, r3, lsl #7 @ encoding: [0x51,0xeb,0xc3,0x10]
|
|
@ CHECK: adc.w r0, r1, r3, lsr #31 @ encoding: [0x41,0xeb,0xd3,0x70]
|
|
@ CHECK: adcs.w r0, r1, r3, asr #32 @ encoding: [0x51,0xeb,0x23,0x00]
|
|
|
|
|
|
@------------------------------------------------------------------------------
|
|
@ ADD (immediate)
|
|
@------------------------------------------------------------------------------
|
|
itet eq
|
|
addeq r1, r2, #4
|
|
addwne r5, r3, #1023
|
|
addeq r4, r5, #293
|
|
add r2, sp, #1024
|
|
add r2, r8, #0xff00
|
|
add r2, r3, #257
|
|
addw r2, r3, #257
|
|
add r12, r6, #0x100
|
|
addw r12, r6, #0x100
|
|
adds r1, r2, #0x1f0
|
|
|
|
@ CHECK: itet eq @ encoding: [0x0a,0xbf]
|
|
@ CHECK: addeq r1, r2, #4 @ encoding: [0x11,0x1d]
|
|
@ CHECK: addwne r5, r3, #1023 @ encoding: [0x03,0xf2,0xff,0x35]
|
|
@ CHECK: addweq r4, r5, #293 @ encoding: [0x05,0xf2,0x25,0x14]
|
|
@ CHECK: add.w r2, sp, #1024 @ encoding: [0x0d,0xf5,0x80,0x62]
|
|
@ CHECK: add.w r2, r8, #65280 @ encoding: [0x08,0xf5,0x7f,0x42]
|
|
@ CHECK: addw r2, r3, #257 @ encoding: [0x03,0xf2,0x01,0x12]
|
|
@ CHECK: addw r2, r3, #257 @ encoding: [0x03,0xf2,0x01,0x12]
|
|
@ CHECK: add.w r12, r6, #256 @ encoding: [0x06,0xf5,0x80,0x7c]
|
|
@ CHECK: addw r12, r6, #256 @ encoding: [0x06,0xf2,0x00,0x1c]
|
|
@ CHECK: adds.w r1, r2, #496 @ encoding: [0x12,0xf5,0xf8,0x71]
|
|
|
|
|
|
@------------------------------------------------------------------------------
|
|
@ FIXME: ADR
|
|
@------------------------------------------------------------------------------
|
|
|
|
|
|
@------------------------------------------------------------------------------
|
|
@ B
|
|
@------------------------------------------------------------------------------
|
|
bmi.w #-183396
|
|
|
|
@ CHECK: bmi.w #-183396 @ encoding: [0x13,0xf5,0xce,0xa9]
|
|
|
|
@------------------------------------------------------------------------------
|
|
@ CBZ/CBNZ
|
|
@------------------------------------------------------------------------------
|
|
cbnz r7, #6
|
|
cbnz r7, #12
|
|
|
|
@ CHECK: cbnz r7, #6 @ encoding: [0x1f,0xb9]
|
|
@ CHECK: cbnz r7, #12 @ encoding: [0x37,0xb9]
|
|
|
|
@------------------------------------------------------------------------------
|
|
@ IT
|
|
@------------------------------------------------------------------------------
|
|
@ Test encodings of a few full IT blocks, not just the IT instruction
|
|
|
|
iteet eq
|
|
addeq r0, r1, r2
|
|
nopne
|
|
subne r5, r6, r7
|
|
addeq r1, r2, #4
|
|
|
|
@ CHECK: iteet eq @ encoding: [0x0d,0xbf]
|
|
@ CHECK: addeq r0, r1, r2 @ encoding: [0x88,0x18]
|
|
@ CHECK: nopne @ encoding: [0x00,0xbf]
|
|
@ CHECK: subne r5, r6, r7 @ encoding: [0xf5,0x1b]
|
|
@ CHECK: addeq r1, r2, #4 @ encoding: [0x11,0x1d]
|