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https://github.com/RPCS3/llvm-mirror.git
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ca0f4dc4f0
This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. llvm-svn: 209577
333 lines
12 KiB
LLVM
333 lines
12 KiB
LLVM
; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
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define <8 x i8> @sqadd8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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;CHECK-LABEL: sqadd8b:
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;CHECK: sqadd.8b
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load <8 x i8>* %B
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%tmp3 = call <8 x i8> @llvm.aarch64.neon.sqadd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
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ret <8 x i8> %tmp3
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}
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define <4 x i16> @sqadd4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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;CHECK-LABEL: sqadd4h:
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;CHECK: sqadd.4h
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%tmp1 = load <4 x i16>* %A
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%tmp2 = load <4 x i16>* %B
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%tmp3 = call <4 x i16> @llvm.aarch64.neon.sqadd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
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ret <4 x i16> %tmp3
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}
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define <2 x i32> @sqadd2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
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;CHECK-LABEL: sqadd2s:
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;CHECK: sqadd.2s
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%tmp1 = load <2 x i32>* %A
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%tmp2 = load <2 x i32>* %B
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%tmp3 = call <2 x i32> @llvm.aarch64.neon.sqadd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
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ret <2 x i32> %tmp3
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}
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define <8 x i8> @uqadd8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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;CHECK-LABEL: uqadd8b:
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;CHECK: uqadd.8b
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load <8 x i8>* %B
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%tmp3 = call <8 x i8> @llvm.aarch64.neon.uqadd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
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ret <8 x i8> %tmp3
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}
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define <4 x i16> @uqadd4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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;CHECK-LABEL: uqadd4h:
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;CHECK: uqadd.4h
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%tmp1 = load <4 x i16>* %A
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%tmp2 = load <4 x i16>* %B
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%tmp3 = call <4 x i16> @llvm.aarch64.neon.uqadd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
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ret <4 x i16> %tmp3
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}
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define <2 x i32> @uqadd2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
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;CHECK-LABEL: uqadd2s:
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;CHECK: uqadd.2s
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%tmp1 = load <2 x i32>* %A
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%tmp2 = load <2 x i32>* %B
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%tmp3 = call <2 x i32> @llvm.aarch64.neon.uqadd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
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ret <2 x i32> %tmp3
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}
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define <16 x i8> @sqadd16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
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;CHECK-LABEL: sqadd16b:
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;CHECK: sqadd.16b
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%tmp1 = load <16 x i8>* %A
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%tmp2 = load <16 x i8>* %B
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%tmp3 = call <16 x i8> @llvm.aarch64.neon.sqadd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
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ret <16 x i8> %tmp3
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}
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define <8 x i16> @sqadd8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
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;CHECK-LABEL: sqadd8h:
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;CHECK: sqadd.8h
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%tmp1 = load <8 x i16>* %A
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%tmp2 = load <8 x i16>* %B
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%tmp3 = call <8 x i16> @llvm.aarch64.neon.sqadd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
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ret <8 x i16> %tmp3
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}
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define <4 x i32> @sqadd4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
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;CHECK-LABEL: sqadd4s:
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;CHECK: sqadd.4s
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%tmp1 = load <4 x i32>* %A
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%tmp2 = load <4 x i32>* %B
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%tmp3 = call <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
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ret <4 x i32> %tmp3
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}
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define <2 x i64> @sqadd2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
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;CHECK-LABEL: sqadd2d:
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;CHECK: sqadd.2d
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%tmp1 = load <2 x i64>* %A
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%tmp2 = load <2 x i64>* %B
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%tmp3 = call <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
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ret <2 x i64> %tmp3
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}
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define <16 x i8> @uqadd16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
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;CHECK-LABEL: uqadd16b:
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;CHECK: uqadd.16b
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%tmp1 = load <16 x i8>* %A
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%tmp2 = load <16 x i8>* %B
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%tmp3 = call <16 x i8> @llvm.aarch64.neon.uqadd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
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ret <16 x i8> %tmp3
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}
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define <8 x i16> @uqadd8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
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;CHECK-LABEL: uqadd8h:
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;CHECK: uqadd.8h
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%tmp1 = load <8 x i16>* %A
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%tmp2 = load <8 x i16>* %B
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%tmp3 = call <8 x i16> @llvm.aarch64.neon.uqadd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
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ret <8 x i16> %tmp3
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}
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define <4 x i32> @uqadd4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
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;CHECK-LABEL: uqadd4s:
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;CHECK: uqadd.4s
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%tmp1 = load <4 x i32>* %A
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%tmp2 = load <4 x i32>* %B
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%tmp3 = call <4 x i32> @llvm.aarch64.neon.uqadd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
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ret <4 x i32> %tmp3
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}
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define <2 x i64> @uqadd2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
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;CHECK-LABEL: uqadd2d:
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;CHECK: uqadd.2d
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%tmp1 = load <2 x i64>* %A
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%tmp2 = load <2 x i64>* %B
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%tmp3 = call <2 x i64> @llvm.aarch64.neon.uqadd.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
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ret <2 x i64> %tmp3
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}
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declare <8 x i8> @llvm.aarch64.neon.sqadd.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
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declare <4 x i16> @llvm.aarch64.neon.sqadd.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
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declare <2 x i32> @llvm.aarch64.neon.sqadd.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
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declare <1 x i64> @llvm.aarch64.neon.sqadd.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
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declare <8 x i8> @llvm.aarch64.neon.uqadd.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
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declare <4 x i16> @llvm.aarch64.neon.uqadd.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
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declare <2 x i32> @llvm.aarch64.neon.uqadd.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
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declare <1 x i64> @llvm.aarch64.neon.uqadd.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
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declare <16 x i8> @llvm.aarch64.neon.sqadd.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
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declare <8 x i16> @llvm.aarch64.neon.sqadd.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
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declare <4 x i32> @llvm.aarch64.neon.sqadd.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
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declare <2 x i64> @llvm.aarch64.neon.sqadd.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
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declare <16 x i8> @llvm.aarch64.neon.uqadd.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
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declare <8 x i16> @llvm.aarch64.neon.uqadd.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
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declare <4 x i32> @llvm.aarch64.neon.uqadd.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
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declare <2 x i64> @llvm.aarch64.neon.uqadd.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
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define <8 x i8> @usqadd8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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;CHECK-LABEL: usqadd8b:
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;CHECK: usqadd.8b
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load <8 x i8>* %B
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%tmp3 = call <8 x i8> @llvm.aarch64.neon.usqadd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
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ret <8 x i8> %tmp3
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}
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define <4 x i16> @usqadd4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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;CHECK-LABEL: usqadd4h:
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;CHECK: usqadd.4h
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%tmp1 = load <4 x i16>* %A
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%tmp2 = load <4 x i16>* %B
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%tmp3 = call <4 x i16> @llvm.aarch64.neon.usqadd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
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ret <4 x i16> %tmp3
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}
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define <2 x i32> @usqadd2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
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;CHECK-LABEL: usqadd2s:
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;CHECK: usqadd.2s
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%tmp1 = load <2 x i32>* %A
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%tmp2 = load <2 x i32>* %B
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%tmp3 = call <2 x i32> @llvm.aarch64.neon.usqadd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
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ret <2 x i32> %tmp3
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}
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define <16 x i8> @usqadd16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
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;CHECK-LABEL: usqadd16b:
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;CHECK: usqadd.16b
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%tmp1 = load <16 x i8>* %A
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%tmp2 = load <16 x i8>* %B
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%tmp3 = call <16 x i8> @llvm.aarch64.neon.usqadd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
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ret <16 x i8> %tmp3
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}
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define <8 x i16> @usqadd8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
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;CHECK-LABEL: usqadd8h:
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;CHECK: usqadd.8h
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%tmp1 = load <8 x i16>* %A
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%tmp2 = load <8 x i16>* %B
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%tmp3 = call <8 x i16> @llvm.aarch64.neon.usqadd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
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ret <8 x i16> %tmp3
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}
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define <4 x i32> @usqadd4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
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;CHECK-LABEL: usqadd4s:
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;CHECK: usqadd.4s
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%tmp1 = load <4 x i32>* %A
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%tmp2 = load <4 x i32>* %B
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%tmp3 = call <4 x i32> @llvm.aarch64.neon.usqadd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
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ret <4 x i32> %tmp3
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}
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define <2 x i64> @usqadd2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
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;CHECK-LABEL: usqadd2d:
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;CHECK: usqadd.2d
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%tmp1 = load <2 x i64>* %A
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%tmp2 = load <2 x i64>* %B
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%tmp3 = call <2 x i64> @llvm.aarch64.neon.usqadd.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
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ret <2 x i64> %tmp3
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}
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define i64 @usqadd_d(i64 %l, i64 %r) nounwind {
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; CHECK-LABEL: usqadd_d:
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; CHECK: usqadd {{d[0-9]+}}, {{d[0-9]+}}
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%sum = call i64 @llvm.aarch64.neon.usqadd.i64(i64 %l, i64 %r)
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ret i64 %sum
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}
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define i32 @usqadd_s(i32 %l, i32 %r) nounwind {
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; CHECK-LABEL: usqadd_s:
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; CHECK: usqadd {{s[0-9]+}}, {{s[0-9]+}}
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%sum = call i32 @llvm.aarch64.neon.usqadd.i32(i32 %l, i32 %r)
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ret i32 %sum
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}
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declare <8 x i8> @llvm.aarch64.neon.usqadd.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
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declare <4 x i16> @llvm.aarch64.neon.usqadd.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
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declare <2 x i32> @llvm.aarch64.neon.usqadd.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
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declare <1 x i64> @llvm.aarch64.neon.usqadd.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
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declare i64 @llvm.aarch64.neon.usqadd.i64(i64, i64) nounwind readnone
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declare i32 @llvm.aarch64.neon.usqadd.i32(i32, i32) nounwind readnone
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declare <16 x i8> @llvm.aarch64.neon.usqadd.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
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declare <8 x i16> @llvm.aarch64.neon.usqadd.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
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declare <4 x i32> @llvm.aarch64.neon.usqadd.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
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declare <2 x i64> @llvm.aarch64.neon.usqadd.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
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define <8 x i8> @suqadd8b(<8 x i8>* %A, <8 x i8>* %B) nounwind {
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;CHECK-LABEL: suqadd8b:
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;CHECK: suqadd.8b
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%tmp1 = load <8 x i8>* %A
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%tmp2 = load <8 x i8>* %B
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%tmp3 = call <8 x i8> @llvm.aarch64.neon.suqadd.v8i8(<8 x i8> %tmp1, <8 x i8> %tmp2)
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ret <8 x i8> %tmp3
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}
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define <4 x i16> @suqadd4h(<4 x i16>* %A, <4 x i16>* %B) nounwind {
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;CHECK-LABEL: suqadd4h:
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;CHECK: suqadd.4h
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%tmp1 = load <4 x i16>* %A
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%tmp2 = load <4 x i16>* %B
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%tmp3 = call <4 x i16> @llvm.aarch64.neon.suqadd.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
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ret <4 x i16> %tmp3
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}
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define <2 x i32> @suqadd2s(<2 x i32>* %A, <2 x i32>* %B) nounwind {
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;CHECK-LABEL: suqadd2s:
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;CHECK: suqadd.2s
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%tmp1 = load <2 x i32>* %A
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%tmp2 = load <2 x i32>* %B
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%tmp3 = call <2 x i32> @llvm.aarch64.neon.suqadd.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
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ret <2 x i32> %tmp3
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}
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define <16 x i8> @suqadd16b(<16 x i8>* %A, <16 x i8>* %B) nounwind {
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;CHECK-LABEL: suqadd16b:
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;CHECK: suqadd.16b
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%tmp1 = load <16 x i8>* %A
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%tmp2 = load <16 x i8>* %B
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%tmp3 = call <16 x i8> @llvm.aarch64.neon.suqadd.v16i8(<16 x i8> %tmp1, <16 x i8> %tmp2)
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ret <16 x i8> %tmp3
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}
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define <8 x i16> @suqadd8h(<8 x i16>* %A, <8 x i16>* %B) nounwind {
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;CHECK-LABEL: suqadd8h:
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;CHECK: suqadd.8h
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%tmp1 = load <8 x i16>* %A
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%tmp2 = load <8 x i16>* %B
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%tmp3 = call <8 x i16> @llvm.aarch64.neon.suqadd.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
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ret <8 x i16> %tmp3
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}
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define <4 x i32> @suqadd4s(<4 x i32>* %A, <4 x i32>* %B) nounwind {
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;CHECK-LABEL: suqadd4s:
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;CHECK: suqadd.4s
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%tmp1 = load <4 x i32>* %A
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%tmp2 = load <4 x i32>* %B
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%tmp3 = call <4 x i32> @llvm.aarch64.neon.suqadd.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
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ret <4 x i32> %tmp3
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}
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define <2 x i64> @suqadd2d(<2 x i64>* %A, <2 x i64>* %B) nounwind {
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;CHECK-LABEL: suqadd2d:
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;CHECK: suqadd.2d
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%tmp1 = load <2 x i64>* %A
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%tmp2 = load <2 x i64>* %B
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%tmp3 = call <2 x i64> @llvm.aarch64.neon.suqadd.v2i64(<2 x i64> %tmp1, <2 x i64> %tmp2)
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ret <2 x i64> %tmp3
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}
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define <1 x i64> @suqadd_1d(<1 x i64> %l, <1 x i64> %r) nounwind {
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; CHECK-LABEL: suqadd_1d:
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; CHECK: suqadd {{d[0-9]+}}, {{d[0-9]+}}
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%sum = call <1 x i64> @llvm.aarch64.neon.suqadd.v1i64(<1 x i64> %l, <1 x i64> %r)
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ret <1 x i64> %sum
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}
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define i64 @suqadd_d(i64 %l, i64 %r) nounwind {
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; CHECK-LABEL: suqadd_d:
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; CHECK: suqadd {{d[0-9]+}}, {{d[0-9]+}}
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%sum = call i64 @llvm.aarch64.neon.suqadd.i64(i64 %l, i64 %r)
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ret i64 %sum
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}
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define i32 @suqadd_s(i32 %l, i32 %r) nounwind {
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; CHECK-LABEL: suqadd_s:
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; CHECK: suqadd {{s[0-9]+}}, {{s[0-9]+}}
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%sum = call i32 @llvm.aarch64.neon.suqadd.i32(i32 %l, i32 %r)
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ret i32 %sum
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}
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declare <8 x i8> @llvm.aarch64.neon.suqadd.v8i8(<8 x i8>, <8 x i8>) nounwind readnone
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declare <4 x i16> @llvm.aarch64.neon.suqadd.v4i16(<4 x i16>, <4 x i16>) nounwind readnone
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declare <2 x i32> @llvm.aarch64.neon.suqadd.v2i32(<2 x i32>, <2 x i32>) nounwind readnone
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declare <1 x i64> @llvm.aarch64.neon.suqadd.v1i64(<1 x i64>, <1 x i64>) nounwind readnone
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declare i64 @llvm.aarch64.neon.suqadd.i64(i64, i64) nounwind readnone
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declare i32 @llvm.aarch64.neon.suqadd.i32(i32, i32) nounwind readnone
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declare <16 x i8> @llvm.aarch64.neon.suqadd.v16i8(<16 x i8>, <16 x i8>) nounwind readnone
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declare <8 x i16> @llvm.aarch64.neon.suqadd.v8i16(<8 x i16>, <8 x i16>) nounwind readnone
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declare <4 x i32> @llvm.aarch64.neon.suqadd.v4i32(<4 x i32>, <4 x i32>) nounwind readnone
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declare <2 x i64> @llvm.aarch64.neon.suqadd.v2i64(<2 x i64>, <2 x i64>) nounwind readnone
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