mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2025-01-31 20:51:52 +01:00
d654e7d40c
Enable enableMultipleCopyHints() on X86. Original Patch by @jonpa: While enabling the mischeduler for SystemZ, it was discovered that for some reason a test needed one extra seemingly needless COPY (test/CodeGen/SystemZ/call-03.ll). The handling for that is resulted in this patch, which improves the register coalescing by providing not just one copy hint, but a sorted list of copy hints. On SystemZ, this gives ~12500 less register moves on SPEC, as well as marginally less spilling. Instead of improving just the SystemZ backend, the improvement has been implemented in common-code (calculateSpillWeightAndHint(). This gives a lot of test failures, but since this should be a general improvement I hope that the involved targets will help and review the test updates. Differential Revision: https://reviews.llvm.org/D38128 llvm-svn: 342578
63 lines
1.6 KiB
LLVM
63 lines
1.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
|
; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s --check-prefix=X86
|
|
; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=X64
|
|
|
|
@a = external global i32
|
|
@b = external global i32
|
|
@c = external global i32
|
|
|
|
define i32 @fn1(i32, i32) {
|
|
; X86-LABEL: fn1:
|
|
; X86: # %bb.0:
|
|
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
|
|
; X86-NEXT: testl %eax, %eax
|
|
; X86-NEXT: je .LBB0_2
|
|
; X86-NEXT: # %bb.1:
|
|
; X86-NEXT: movl {{[0-9]+}}(%esp), %eax
|
|
; X86-NEXT: .LBB0_2:
|
|
; X86-NEXT: retl
|
|
;
|
|
; X64-LABEL: fn1:
|
|
; X64: # %bb.0:
|
|
; X64-NEXT: movl %edi, %eax
|
|
; X64-NEXT: testl %esi, %esi
|
|
; X64-NEXT: cmovel %esi, %eax
|
|
; X64-NEXT: retq
|
|
%3 = icmp ne i32 %1, 0
|
|
%4 = select i1 %3, i32 %0, i32 0
|
|
ret i32 %4
|
|
}
|
|
|
|
define void @fn2() {
|
|
; X86-LABEL: fn2:
|
|
; X86: # %bb.0:
|
|
; X86-NEXT: movl b, %eax
|
|
; X86-NEXT: decl a
|
|
; X86-NEXT: jne .LBB1_2
|
|
; X86-NEXT: # %bb.1:
|
|
; X86-NEXT: xorl %eax, %eax
|
|
; X86-NEXT: .LBB1_2:
|
|
; X86-NEXT: movl %eax, c
|
|
; X86-NEXT: retl
|
|
;
|
|
; X64-LABEL: fn2:
|
|
; X64: # %bb.0:
|
|
; X64-NEXT: xorl %eax, %eax
|
|
; X64-NEXT: decl {{.*}}(%rip)
|
|
; X64-NEXT: je .LBB1_2
|
|
; X64-NEXT: # %bb.1:
|
|
; X64-NEXT: movl {{.*}}(%rip), %eax
|
|
; X64-NEXT: .LBB1_2:
|
|
; X64-NEXT: movl %eax, {{.*}}(%rip)
|
|
; X64-NEXT: retq
|
|
%1 = load volatile i32, i32* @b, align 4
|
|
%2 = load i32, i32* @a, align 4
|
|
%3 = add nsw i32 %2, -1
|
|
store i32 %3, i32* @a, align 4
|
|
%4 = icmp ne i32 %3, 0
|
|
%5 = select i1 %4, i32 %1, i32 0
|
|
store i32 %5, i32* @c, align 4
|
|
ret void
|
|
}
|
|
|