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llvm-mirror/test/CodeGen/X86/select-1-or-neg1.ll
Craig Topper 6ee1e349e5 [X86] Support LEA64_32r in processInstrForSlow3OpLEA and use INC/DEC when possible.
Move the erasing and iterator updating inside to match the
other slow LEA function.

I've adapted code from optTwoAddrLEA and basically rebuilt the
implementation here. We do lose the kill flags now just like
optTwoAddrLEA. This runs late enough in the pipeline that
shouldn't really be a problem.

llvm-svn: 373877
2019-10-07 06:27:55 +00:00

30 lines
952 B
LLVM

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=BASE
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=slow-3ops-lea | FileCheck %s --check-prefix=SLOWLEA3
; TODO: Should the 'cmpl' be 'dec' instead?
; TODO: What if 'cmov' is 1 uop and full throughput (Ryzen)?
define i32 @PR28968(i32 %x) {
; BASE-LABEL: PR28968:
; BASE: # %bb.0:
; BASE-NEXT: xorl %eax, %eax
; BASE-NEXT: cmpl $1, %edi
; BASE-NEXT: sete %al
; BASE-NEXT: leal -1(%rax,%rax), %eax
; BASE-NEXT: retq
;
; SLOWLEA3-LABEL: PR28968:
; SLOWLEA3: # %bb.0:
; SLOWLEA3-NEXT: xorl %eax, %eax
; SLOWLEA3-NEXT: cmpl $1, %edi
; SLOWLEA3-NEXT: sete %al
; SLOWLEA3-NEXT: addl %eax, %eax
; SLOWLEA3-NEXT: decl %eax
; SLOWLEA3-NEXT: retq
%cmp = icmp eq i32 %x, 1
%sel = select i1 %cmp, i32 1, i32 -1
ret i32 %sel
}