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0663a19f9d
The assert that caused this to be reverted should be fixed now. Original commit message: This patch changes our defualt legalization behavior for 16, 32, and 64 bit vectors with i8/i16/i32/i64 scalar types from promotion to widening. For example, v8i8 will now be widened to v16i8 instead of promoted to v8i16. This keeps the elements widths the same and pads with undef elements. We believe this is a better legalization strategy. But it carries some issues due to the fragmented vector ISA. For example, i8 shifts and multiplies get widened and then later have to be promoted/split into vXi16 vectors. This has the potential to cause regressions so we wanted to get it in early in the 10.0 cycle so we have plenty of time to address them. Next steps will be to merge tests that explicitly test the command line option. And then we can remove the option and its associated code. llvm-svn: 368183
99 lines
3.3 KiB
LLVM
99 lines
3.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=i386-apple-darwin10.0 | FileCheck %s --check-prefix=CHECK-X86
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; RUN: llc < %s -mtriple=x86_64-grtev4-linux-gnu | FileCheck %s --check-prefix=CHECK-X64
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@g_14 = global i8 -6, align 1 ; <i8*> [#uses=1]
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declare i32 @func_16(i8 signext %p_19, i32 %p_20) nounwind
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define i32 @func_35(i64 %p_38) nounwind ssp {
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; CHECK-X86-LABEL: func_35:
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; CHECK-X86: ## %bb.0: ## %entry
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; CHECK-X86-NEXT: subl $12, %esp
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; CHECK-X86-NEXT: movsbl _g_14, %eax
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; CHECK-X86-NEXT: xorl %ecx, %ecx
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; CHECK-X86-NEXT: testl $255, %eax
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; CHECK-X86-NEXT: setg %cl
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; CHECK-X86-NEXT: subl $8, %esp
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; CHECK-X86-NEXT: pushl %ecx
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; CHECK-X86-NEXT: pushl %eax
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; CHECK-X86-NEXT: calll _func_16
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; CHECK-X86-NEXT: addl $16, %esp
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; CHECK-X86-NEXT: movl $1, %eax
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; CHECK-X86-NEXT: addl $12, %esp
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; CHECK-X86-NEXT: retl
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;
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; CHECK-X64-LABEL: func_35:
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; CHECK-X64: # %bb.0: # %entry
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; CHECK-X64-NEXT: pushq %rax
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; CHECK-X64-NEXT: movsbl {{.*}}(%rip), %edi
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; CHECK-X64-NEXT: xorl %esi, %esi
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; CHECK-X64-NEXT: testl $255, %edi
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; CHECK-X64-NEXT: setg %sil
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; CHECK-X64-NEXT: callq func_16
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; CHECK-X64-NEXT: movl $1, %eax
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; CHECK-X64-NEXT: popq %rcx
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; CHECK-X64-NEXT: retq
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entry:
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%tmp = load i8, i8* @g_14 ; <i8> [#uses=2]
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%conv = zext i8 %tmp to i32 ; <i32> [#uses=1]
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%cmp = icmp sle i32 1, %conv ; <i1> [#uses=1]
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%conv2 = zext i1 %cmp to i32 ; <i32> [#uses=1]
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%call = call i32 @func_16(i8 signext %tmp, i32 %conv2) ssp ; <i32> [#uses=1]
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ret i32 1
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}
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define void @fail(i16 %a, <2 x i8> %b) {
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; CHECK-X86-LABEL: fail:
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; CHECK-X86: ## %bb.0:
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; CHECK-X86-NEXT: subl $12, %esp
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; CHECK-X86-NEXT: .cfi_def_cfa_offset 16
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; CHECK-X86-NEXT: movzwl {{[0-9]+}}(%esp), %ecx
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; CHECK-X86-NEXT: cmpb $123, {{[0-9]+}}(%esp)
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; CHECK-X86-NEXT: sete %al
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; CHECK-X86-NEXT: testl $263, %ecx ## imm = 0x107
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; CHECK-X86-NEXT: je LBB1_3
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; CHECK-X86-NEXT: ## %bb.1:
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; CHECK-X86-NEXT: testb %al, %al
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; CHECK-X86-NEXT: jne LBB1_3
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; CHECK-X86-NEXT: ## %bb.2: ## %no
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; CHECK-X86-NEXT: calll _bar
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; CHECK-X86-NEXT: LBB1_3: ## %yes
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; CHECK-X86-NEXT: addl $12, %esp
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; CHECK-X86-NEXT: retl
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;
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; CHECK-X64-LABEL: fail:
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; CHECK-X64: # %bb.0:
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; CHECK-X64-NEXT: pushq %rax
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; CHECK-X64-NEXT: .cfi_def_cfa_offset 16
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; CHECK-X64-NEXT: testl $263, %edi # imm = 0x107
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; CHECK-X64-NEXT: je .LBB1_3
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; CHECK-X64-NEXT: # %bb.1:
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; CHECK-X64-NEXT: pcmpeqb {{.*}}(%rip), %xmm0
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; CHECK-X64-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
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; CHECK-X64-NEXT: pextrw $1, %xmm0, %eax
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; CHECK-X64-NEXT: testb $1, %al
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; CHECK-X64-NEXT: jne .LBB1_3
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; CHECK-X64-NEXT: # %bb.2: # %no
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; CHECK-X64-NEXT: callq bar
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; CHECK-X64-NEXT: .LBB1_3: # %yes
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; CHECK-X64-NEXT: popq %rax
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; CHECK-X64-NEXT: .cfi_def_cfa_offset 8
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; CHECK-X64-NEXT: retq
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%1 = icmp eq <2 x i8> %b, <i8 40, i8 123>
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%2 = extractelement <2 x i1> %1, i32 1
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%3 = and i16 %a, 263
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%4 = icmp eq i16 %3, 0
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%merge = or i1 %4, %2
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br i1 %merge, label %yes, label %no
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yes: ; preds = %0
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ret void
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no: ; preds = %0
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call void @bar()
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ret void
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}
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declare void @bar()
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