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llvm-mirror/test/CodeGen/MIR/X86/mir-namer-hash-frameindex.mir
Puyan Lotfi d98b5ce834 [llvm][MIRVRegNamerUtils] Adding hashing on FrameIndex MachineOperands.
This patch makes it so that cases where multiple instructions that differ only
in their FrameIndex MachineOperand values no longer collide. For instance:

%1:_(p0) = G_FRAME_INDEX %stack.0
%2:_(p0) = G_FRAME_INDEX %stack.1

Prior to this patch these instructions would collide together.

Differential Revision: https://reviews.llvm.org/D71583
2020-01-13 13:39:54 -05:00

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YAML

# RUN: llc -mtriple x86_64-linux-gnu -run-pass mir-canonicalizer -verify-machineinstrs %s -o - | FileCheck %s
...
---
name: f
stack:
- { id: 0, size: 4 }
- { id: 1, size: 4 }
fixedStack:
- { id: 0, offset: 0, size: 4 }
- { id: 1, offset: 0, size: 4 }
body: |
bb.1:
; CHECK: _1:_(p0) = G_FRAME_INDEX %stack.{{[0-1]}}
; CHECK: _1:_(p0) = G_FRAME_INDEX %stack.{{[0-1]}}
; CHECK: _1:gr32 = MOV32rm %fixed-stack.{{[0-1]}}
; CHECK: _1:gr32 = MOV32rm %fixed-stack.{{[0-1]}}
%1:_(p0) = G_FRAME_INDEX %stack.0
%2:_(p0) = G_FRAME_INDEX %stack.1
%3:gr32 = MOV32rm %fixed-stack.0, 1, _, 0, _
%4:gr32 = MOV32rm %fixed-stack.1, 1, _, 0, _
...