mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-23 11:13:28 +01:00
d4c615be8c
Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
43 lines
906 B
YAML
43 lines
906 B
YAML
# RUN: llc -run-pass=aarch64-expand-pseudo %s -o - | FileCheck %s
|
|
|
|
--- |
|
|
; ModuleID = 'simple.ll'
|
|
source_filename = "simple.ll"
|
|
target datalayout = "e-m:e-i64:64-i128:128-n32:64-S128"
|
|
target triple = "aarch64--linux-gnu"
|
|
|
|
define i32 @test_mov_0() {
|
|
ret i32 42
|
|
}
|
|
|
|
...
|
|
---
|
|
name: test_mov_0
|
|
alignment: 2
|
|
exposesReturnsTwice: false
|
|
tracksRegLiveness: false
|
|
frameInfo:
|
|
isFrameAddressTaken: false
|
|
isReturnAddressTaken: false
|
|
hasStackMap: false
|
|
hasPatchPoint: false
|
|
stackSize: 0
|
|
offsetAdjustment: 0
|
|
maxAlignment: 0
|
|
adjustsStack: false
|
|
hasCalls: false
|
|
maxCallFrameSize: 0
|
|
hasOpaqueSPAdjustment: false
|
|
hasVAStart: false
|
|
hasMustTailInVarArgFunc: false
|
|
body: |
|
|
bb.0 (%ir-block.0):
|
|
$wzr = MOVi32imm 42
|
|
$xzr = MOVi64imm 42
|
|
RET_ReallyLR implicit killed $w0
|
|
|
|
...
|
|
|
|
# CHECK: bb.0
|
|
# CHECK-NEXT: RET undef $lr
|