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llvm-mirror/test/CodeGen/X86/mmx-vzmovl.ll
Dale Johannesen 4d1ca2ab29 Mark all these as needing SSE2. Should fix PPC and
maybe even Linux.

llvm-svn: 115291
2010-10-01 04:17:55 +00:00

16 lines
548 B
LLVM

; RUN: llc < %s -march=x86-64 -mattr=+mmx,+sse2 | grep movq | count 2
; There are no MMX operations here; this is promoted to XMM.
define void @foo(<1 x i64>* %a, <1 x i64>* %b) nounwind {
entry:
%0 = load <1 x i64>* %a, align 8 ; <<1 x i64>> [#uses=1]
%1 = bitcast <1 x i64> %0 to <2 x i32> ; <<2 x i32>> [#uses=1]
%2 = and <2 x i32> %1, < i32 -1, i32 0 > ; <<2 x i32>> [#uses=1]
%3 = bitcast <2 x i32> %2 to <1 x i64> ; <<1 x i64>> [#uses=1]
store <1 x i64> %3, <1 x i64>* %b, align 8
br label %bb2
bb2: ; preds = %entry
ret void
}