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144efa4313
X86EvexToVex machine instruction pass compresses EVEX encoded instructions by replacing them with their identical VEX encoded instructions when possible. It uses manually supported 2 large tables that map the EVEX instructions to their VEX ideticals. This TableGen backend replaces the tables by automatically generating them. Differential Revision: https://reviews.llvm.org/D30451 llvm-svn: 297127
43 lines
964 B
CMake
43 lines
964 B
CMake
set(LLVM_LINK_COMPONENTS Support)
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add_tablegen(llvm-tblgen LLVM
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AsmMatcherEmitter.cpp
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AsmWriterEmitter.cpp
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AsmWriterInst.cpp
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Attributes.cpp
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CallingConvEmitter.cpp
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CodeEmitterGen.cpp
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CodeGenDAGPatterns.cpp
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CodeGenInstruction.cpp
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CodeGenMapTable.cpp
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CodeGenRegisters.cpp
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CodeGenSchedule.cpp
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CodeGenTarget.cpp
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DAGISelEmitter.cpp
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DAGISelMatcherEmitter.cpp
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DAGISelMatcherGen.cpp
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DAGISelMatcherOpt.cpp
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DAGISelMatcher.cpp
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DFAPacketizerEmitter.cpp
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DisassemblerEmitter.cpp
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FastISelEmitter.cpp
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FixedLenDecoderEmitter.cpp
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GlobalISelEmitter.cpp
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InstrInfoEmitter.cpp
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IntrinsicEmitter.cpp
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OptParserEmitter.cpp
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PseudoLoweringEmitter.cpp
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RegisterBankEmitter.cpp
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RegisterInfoEmitter.cpp
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SearchableTableEmitter.cpp
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SubtargetEmitter.cpp
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SubtargetFeatureInfo.cpp
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TableGen.cpp
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Types.cpp
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X86DisassemblerTables.cpp
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X86EVEX2VEXTablesEmitter.cpp
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X86ModRMFilters.cpp
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X86RecognizableInstr.cpp
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CTagsEmitter.cpp
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)
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