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bdc6e663e7
This patch adds support for struct return values to the MSP430 target backend. It also reverses the order of argument and return registers in the calling convention to bring it into closer alignment with the published EABI from TI. Patch by Andrew Wygle (awygle). Differential Revision: https://reviews.llvm.org/D29069 llvm-svn: 296807
115 lines
2.4 KiB
LLVM
115 lines
2.4 KiB
LLVM
; RUN: llc -march=msp430 < %s | FileCheck %s
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target datalayout = "e-p:16:16:16-i1:8:8-i8:8:8-i16:16:16-i32:16:32"
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target triple = "msp430-generic-generic"
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define i16 @sccweqand(i16 %a, i16 %b) nounwind {
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%t1 = and i16 %a, %b
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%t2 = icmp eq i16 %t1, 0
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%t3 = zext i1 %t2 to i16
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ret i16 %t3
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}
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; CHECK-LABEL: sccweqand:
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; CHECK: bit.w r13, r12
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; CHECK: mov.w r2, r12
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; CHECK: rra.w r12
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; CHECK: and.w #1, r12
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define i16 @sccwneand(i16 %a, i16 %b) nounwind {
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%t1 = and i16 %a, %b
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%t2 = icmp ne i16 %t1, 0
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%t3 = zext i1 %t2 to i16
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ret i16 %t3
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}
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; CHECK-LABEL: sccwneand:
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; CHECK: bit.w r13, r12
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; CHECK: mov.w r2, r12
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; CHECK: and.w #1, r12
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define i16 @sccwne(i16 %a, i16 %b) nounwind {
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%t1 = icmp ne i16 %a, %b
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%t2 = zext i1 %t1 to i16
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ret i16 %t2
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}
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; CHECK-LABEL:sccwne:
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; CHECK: cmp.w r13, r12
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; CHECK: mov.w r2, r13
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; CHECK: rra.w r13
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; CHECK: mov.w #1, r12
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; CHECK: bic.w r13, r12
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define i16 @sccweq(i16 %a, i16 %b) nounwind {
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%t1 = icmp eq i16 %a, %b
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%t2 = zext i1 %t1 to i16
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ret i16 %t2
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}
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; CHECK-LABEL:sccweq:
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; CHECK: cmp.w r13, r12
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; CHECK: mov.w r2, r12
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; CHECK: rra.w r12
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; CHECK: and.w #1, r12
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define i16 @sccwugt(i16 %a, i16 %b) nounwind {
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%t1 = icmp ugt i16 %a, %b
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%t2 = zext i1 %t1 to i16
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ret i16 %t2
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}
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; CHECK-LABEL:sccwugt:
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; CHECK: cmp.w r12, r13
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; CHECK: mov.w #1, r12
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; CHECK: bic.w r2, r12
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define i16 @sccwuge(i16 %a, i16 %b) nounwind {
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%t1 = icmp uge i16 %a, %b
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%t2 = zext i1 %t1 to i16
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ret i16 %t2
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}
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; CHECK-LABEL:sccwuge:
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; CHECK: cmp.w r13, r12
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; CHECK: mov.w r2, r12
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; CHECK: and.w #1, r12
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define i16 @sccwult(i16 %a, i16 %b) nounwind {
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%t1 = icmp ult i16 %a, %b
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%t2 = zext i1 %t1 to i16
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ret i16 %t2
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}
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; CHECK-LABEL:sccwult:
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; CHECK: cmp.w r13, r12
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; CHECK: mov.w #1, r12
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; CHECK: bic.w r2, r12
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define i16 @sccwule(i16 %a, i16 %b) nounwind {
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%t1 = icmp ule i16 %a, %b
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%t2 = zext i1 %t1 to i16
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ret i16 %t2
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}
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; CHECK-LABEL:sccwule:
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; CHECK: cmp.w r12, r13
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; CHECK: mov.w r2, r12
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; CHECK: and.w #1, r12
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define i16 @sccwsgt(i16 %a, i16 %b) nounwind {
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%t1 = icmp sgt i16 %a, %b
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%t2 = zext i1 %t1 to i16
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ret i16 %t2
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}
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define i16 @sccwsge(i16 %a, i16 %b) nounwind {
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%t1 = icmp sge i16 %a, %b
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%t2 = zext i1 %t1 to i16
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ret i16 %t2
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}
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define i16 @sccwslt(i16 %a, i16 %b) nounwind {
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%t1 = icmp slt i16 %a, %b
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%t2 = zext i1 %t1 to i16
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ret i16 %t2
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}
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define i16 @sccwsle(i16 %a, i16 %b) nounwind {
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%t1 = icmp sle i16 %a, %b
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%t2 = zext i1 %t1 to i16
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ret i16 %t2
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}
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