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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-23 13:02:52 +02:00
llvm-mirror/test/CodeGen
2017-03-22 23:10:46 +00:00
..
AArch64 [GlobalISel]: Create VREGs for ConstantInt args 2017-03-22 01:16:39 +00:00
AMDGPU [AMDGPU] Emit kernel debug properties as code object metadata 2017-03-22 23:10:46 +00:00
ARM [GlobalISel] Fix shufflevector tests 2017-03-21 13:12:59 +00:00
AVR
BPF
Generic Fix constant folding of fp2int to large integers 2017-03-19 16:50:25 +00:00
Hexagon Recommit r298282 with fixes for memory allocation/deallocation 2017-03-21 17:09:27 +00:00
Inputs
Lanai
Mips CodeGen: BlockPlacement: Reduce TriangleChainCount to 2 2017-03-16 01:32:29 +00:00
MIR AMDGPU: Mark all unspecified CC functions in tests as amdgpu_kernel 2017-03-21 21:39:51 +00:00
MSP430
NVPTX [SelectionDAG] Optimize VSELECT->SETCC of incompatible or illegal types. 2017-03-16 07:17:12 +00:00
PowerPC CalleeSavedRegister was removed from MIR and is recalculated upon MIR parsing. 2017-03-19 11:18:09 +00:00
SPARC
SystemZ [SystemZ] Don't drop any operands in expandZExtPseudo() 2017-03-22 06:03:32 +00:00
Thumb [ARM] t2_so_imm_neg had a subtle bug in the conversion, and could trigger UB by negating (int)-2147483648. By pure luck, none of the pre-existing tests triggered this; so I'm adding one. 2017-03-22 15:09:30 +00:00
Thumb2
WebAssembly
WinEH
X86 [x86] improve tests, add tests, auto-generate checks; NFC 2017-03-22 22:39:17 +00:00
XCore