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d7f173214f
I'm doing this in two phases for a better "git blame" record. This commit removes the previous AArch64 backend and redirects all functionality to ARM64. It also deduplicates test-lines and removes orphaned AArch64 tests. The next step will be "git mv ARM64 AArch64" and rewire most of the tests. Hopefully LLVM is still functional, though it would be even better if no-one ever had to care because the rename happens straight afterwards. llvm-svn: 209576
66 lines
1.6 KiB
LLVM
66 lines
1.6 KiB
LLVM
; RUN: llc -verify-machineinstrs < %s -mtriple=arm64-apple-ios7.0 | FileCheck --check-prefix=CHECK --check-prefix=CHECK-LE %s
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; RUN: llc -verify-machineinstrs < %s -mtriple=arm64_be-none-linux-gnu | FileCheck --check-prefix=CHECK --check-prefix=CHECK-BE %s
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define i128 @test_simple(i128 %a, i128 %b, i128 %c) {
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; CHECK-LABEL: test_simple:
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%valadd = add i128 %a, %b
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; CHECK-LE: adds [[ADDLO:x[0-9]+]], x0, x2
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; CHECK-LE-NEXT: adcs [[ADDHI:x[0-9]+]], x1, x3
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; CHECK-BE: adds [[ADDLO:x[0-9]+]], x1, x3
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; CHECK-BE-NEXT: adcs [[ADDHI:x[0-9]+]], x0, x2
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%valsub = sub i128 %valadd, %c
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; CHECK-LE: subs x0, [[ADDLO]], x4
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; CHECK-LE: sbcs x1, [[ADDHI]], x5
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; CHECK-BE: subs x1, [[ADDLO]], x5
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; CHECK-BE: sbcs x0, [[ADDHI]], x4
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ret i128 %valsub
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; CHECK: ret
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}
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define i128 @test_imm(i128 %a) {
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; CHECK-LABEL: test_imm:
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%val = add i128 %a, 12
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; CHECK-LE: adds x0, x0, #12
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; CHECK-LE: adcs x1, x1, {{x[0-9]|xzr}}
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; CHECK-BE: adds x1, x1, #12
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; CHECK-BE: adcs x0, x0, {{x[0-9]|xzr}}
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ret i128 %val
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; CHECK: ret
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}
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define i128 @test_shifted(i128 %a, i128 %b) {
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; CHECK-LABEL: test_shifted:
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%rhs = shl i128 %b, 45
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%val = add i128 %a, %rhs
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; CHECK-LE: adds x0, x0, x2, lsl #45
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; CHECK-LE: adcs x1, x1, {{x[0-9]}}
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; CHECK-BE: adds x1, x1, x3, lsl #45
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; CHECK-BE: adcs x0, x0, {{x[0-9]}}
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ret i128 %val
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; CHECK: ret
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}
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define i128 @test_extended(i128 %a, i16 %b) {
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; CHECK-LABEL: test_extended:
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%ext = sext i16 %b to i128
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%rhs = shl i128 %ext, 3
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%val = add i128 %a, %rhs
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; CHECK-LE: adds x0, x0, w2, sxth #3
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; CHECK-LE: adcs x1, x1, {{x[0-9]}}
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; CHECK-BE: adds x1, x1, w2, sxth #3
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; CHECK-BE: adcs x0, x0, {{x[0-9]}}
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ret i128 %val
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; CHECK: ret
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}
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