mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-29 23:12:55 +01:00
b9ec29d7c5
This commit adds a weak variant of the cmpxchg operation, as described
in C++11. A cmpxchg instruction with this modifier is permitted to
fail to store, even if the comparison indicated it should.
As a result, cmpxchg instructions must return a flag indicating
success in addition to their original iN value loaded. Thus, for
uniformity *all* cmpxchg instructions now return "{ iN, i1 }". The
second flag is 1 when the store succeeded.
At the DAG level, a new ATOMIC_CMP_SWAP_WITH_SUCCESS node has been
added as the natural representation for the new cmpxchg instructions.
It is a strong cmpxchg.
By default this gets Expanded to the existing ATOMIC_CMP_SWAP during
Legalization, so existing backends should see no change in behaviour.
If they wish to deal with the enhanced node instead, they can call
setOperationAction on it. Beware: as a node with 2 results, it cannot
be selected from TableGen.
Currently, no use is made of the extra information provided in this
patch. Test updates are almost entirely adapting the input IR to the
new scheme.
Summary for out of tree users:
------------------------------
+ Legacy Bitcode files are upgraded during read.
+ Legacy assembly IR files will be invalid.
+ Front-ends must adapt to different type for "cmpxchg".
+ Backends should be unaffected by default.
llvm-svn: 210903
334 lines
11 KiB
LLVM
334 lines
11 KiB
LLVM
; RUN: llc < %s -march=arm64 -verify-machineinstrs -mcpu=cyclone | FileCheck %s
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define i32 @val_compare_and_swap(i32* %p) {
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; CHECK-LABEL: val_compare_and_swap:
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; CHECK: orr [[NEWVAL_REG:w[0-9]+]], wzr, #0x4
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; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
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; CHECK: ldaxr [[RESULT:w[0-9]+]], [x0]
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; CHECK: cmp [[RESULT]], #7
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; CHECK: b.ne [[LABEL2:.?LBB[0-9]+_[0-9]+]]
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; CHECK: stxr [[SCRATCH_REG:w[0-9]+]], [[NEWVAL_REG]], [x0]
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; CHECK: cbnz [[SCRATCH_REG]], [[LABEL]]
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; CHECK: [[LABEL2]]:
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%pair = cmpxchg i32* %p, i32 7, i32 4 acquire acquire
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%val = extractvalue { i32, i1 } %pair, 0
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ret i32 %val
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}
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define i64 @val_compare_and_swap_64(i64* %p) {
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; CHECK-LABEL: val_compare_and_swap_64:
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; CHECK: orr w[[NEWVAL_REG:[0-9]+]], wzr, #0x4
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; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
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; CHECK: ldxr [[RESULT:x[0-9]+]], [x0]
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; CHECK: cmp [[RESULT]], #7
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; CHECK: b.ne [[LABEL2:.?LBB[0-9]+_[0-9]+]]
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; CHECK-NOT: stxr x[[NEWVAL_REG]], x[[NEWVAL_REG]]
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; CHECK: stxr [[SCRATCH_REG:w[0-9]+]], x[[NEWVAL_REG]], [x0]
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; CHECK: cbnz [[SCRATCH_REG]], [[LABEL]]
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; CHECK: [[LABEL2]]:
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%pair = cmpxchg i64* %p, i64 7, i64 4 monotonic monotonic
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%val = extractvalue { i64, i1 } %pair, 0
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ret i64 %val
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}
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define i32 @fetch_and_nand(i32* %p) {
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; CHECK-LABEL: fetch_and_nand:
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; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
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; CHECK: ldxr w[[DEST_REG:[0-9]+]], [x0]
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; CHECK: and [[SCRATCH2_REG:w[0-9]+]], w[[DEST_REG]], #0xfffffff8
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; CHECK-NOT: stlxr [[SCRATCH2_REG]], [[SCRATCH2_REG]]
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; CHECK: stlxr [[SCRATCH_REG:w[0-9]+]], [[SCRATCH2_REG]], [x0]
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; CHECK: cbnz [[SCRATCH_REG]], [[LABEL]]
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; CHECK: mov x0, x[[DEST_REG]]
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%val = atomicrmw nand i32* %p, i32 7 release
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ret i32 %val
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}
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define i64 @fetch_and_nand_64(i64* %p) {
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; CHECK-LABEL: fetch_and_nand_64:
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; CHECK: mov x[[ADDR:[0-9]+]], x0
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; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
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; CHECK: ldaxr [[DEST_REG:x[0-9]+]], [x[[ADDR]]]
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; CHECK: and [[SCRATCH2_REG:x[0-9]+]], [[DEST_REG]], #0xfffffffffffffff8
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; CHECK: stlxr [[SCRATCH_REG:w[0-9]+]], [[SCRATCH2_REG]], [x[[ADDR]]]
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; CHECK: cbnz [[SCRATCH_REG]], [[LABEL]]
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%val = atomicrmw nand i64* %p, i64 7 acq_rel
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ret i64 %val
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}
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define i32 @fetch_and_or(i32* %p) {
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; CHECK-LABEL: fetch_and_or:
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; CHECK: movz [[OLDVAL_REG:w[0-9]+]], #0x5
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; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
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; CHECK: ldaxr w[[DEST_REG:[0-9]+]], [x0]
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; CHECK: orr [[SCRATCH2_REG:w[0-9]+]], w[[DEST_REG]], [[OLDVAL_REG]]
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; CHECK-NOT: stlxr [[SCRATCH2_REG]], [[SCRATCH2_REG]]
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; CHECK: stlxr [[SCRATCH_REG:w[0-9]+]], [[SCRATCH2_REG]], [x0]
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; CHECK: cbnz [[SCRATCH_REG]], [[LABEL]]
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; CHECK: mov x0, x[[DEST_REG]]
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%val = atomicrmw or i32* %p, i32 5 seq_cst
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ret i32 %val
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}
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define i64 @fetch_and_or_64(i64* %p) {
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; CHECK: fetch_and_or_64:
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; CHECK: mov x[[ADDR:[0-9]+]], x0
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; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
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; CHECK: ldxr [[DEST_REG:x[0-9]+]], [x[[ADDR]]]
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; CHECK: orr [[SCRATCH2_REG:x[0-9]+]], [[DEST_REG]], #0x7
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; CHECK: stxr [[SCRATCH_REG:w[0-9]+]], [[SCRATCH2_REG]], [x[[ADDR]]]
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; CHECK: cbnz [[SCRATCH_REG]], [[LABEL]]
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%val = atomicrmw or i64* %p, i64 7 monotonic
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ret i64 %val
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}
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define void @acquire_fence() {
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fence acquire
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ret void
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; CHECK-LABEL: acquire_fence:
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; CHECK: dmb ishld
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}
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define void @release_fence() {
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fence release
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ret void
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; CHECK-LABEL: release_fence:
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; CHECK: dmb ish{{$}}
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}
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define void @seq_cst_fence() {
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fence seq_cst
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ret void
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; CHECK-LABEL: seq_cst_fence:
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; CHECK: dmb ish{{$}}
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}
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define i32 @atomic_load(i32* %p) {
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%r = load atomic i32* %p seq_cst, align 4
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ret i32 %r
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; CHECK-LABEL: atomic_load:
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; CHECK: ldar
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}
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define i8 @atomic_load_relaxed_8(i8* %p, i32 %off32) {
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; CHECK-LABEL: atomic_load_relaxed_8:
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%ptr_unsigned = getelementptr i8* %p, i32 4095
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%val_unsigned = load atomic i8* %ptr_unsigned monotonic, align 1
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; CHECK: ldrb {{w[0-9]+}}, [x0, #4095]
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%ptr_regoff = getelementptr i8* %p, i32 %off32
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%val_regoff = load atomic i8* %ptr_regoff unordered, align 1
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%tot1 = add i8 %val_unsigned, %val_regoff
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; CHECK: ldrb {{w[0-9]+}}, [x0, w1, sxtw]
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%ptr_unscaled = getelementptr i8* %p, i32 -256
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%val_unscaled = load atomic i8* %ptr_unscaled monotonic, align 1
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%tot2 = add i8 %tot1, %val_unscaled
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; CHECK: ldurb {{w[0-9]+}}, [x0, #-256]
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%ptr_random = getelementptr i8* %p, i32 1191936 ; 0x123000 (i.e. ADD imm)
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%val_random = load atomic i8* %ptr_random unordered, align 1
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%tot3 = add i8 %tot2, %val_random
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; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
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; CHECK: ldrb {{w[0-9]+}}, [x[[ADDR]]]
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ret i8 %tot3
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}
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define i16 @atomic_load_relaxed_16(i16* %p, i32 %off32) {
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; CHECK-LABEL: atomic_load_relaxed_16:
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%ptr_unsigned = getelementptr i16* %p, i32 4095
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%val_unsigned = load atomic i16* %ptr_unsigned monotonic, align 2
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; CHECK: ldrh {{w[0-9]+}}, [x0, #8190]
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%ptr_regoff = getelementptr i16* %p, i32 %off32
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%val_regoff = load atomic i16* %ptr_regoff unordered, align 2
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%tot1 = add i16 %val_unsigned, %val_regoff
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; CHECK: ldrh {{w[0-9]+}}, [x0, w1, sxtw #1]
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%ptr_unscaled = getelementptr i16* %p, i32 -128
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%val_unscaled = load atomic i16* %ptr_unscaled monotonic, align 2
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%tot2 = add i16 %tot1, %val_unscaled
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; CHECK: ldurh {{w[0-9]+}}, [x0, #-256]
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%ptr_random = getelementptr i16* %p, i32 595968 ; 0x123000/2 (i.e. ADD imm)
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%val_random = load atomic i16* %ptr_random unordered, align 2
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%tot3 = add i16 %tot2, %val_random
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; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
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; CHECK: ldrh {{w[0-9]+}}, [x[[ADDR]]]
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ret i16 %tot3
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}
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define i32 @atomic_load_relaxed_32(i32* %p, i32 %off32) {
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; CHECK-LABEL: atomic_load_relaxed_32:
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%ptr_unsigned = getelementptr i32* %p, i32 4095
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%val_unsigned = load atomic i32* %ptr_unsigned monotonic, align 4
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; CHECK: ldr {{w[0-9]+}}, [x0, #16380]
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%ptr_regoff = getelementptr i32* %p, i32 %off32
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%val_regoff = load atomic i32* %ptr_regoff unordered, align 4
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%tot1 = add i32 %val_unsigned, %val_regoff
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; CHECK: ldr {{w[0-9]+}}, [x0, w1, sxtw #2]
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%ptr_unscaled = getelementptr i32* %p, i32 -64
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%val_unscaled = load atomic i32* %ptr_unscaled monotonic, align 4
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%tot2 = add i32 %tot1, %val_unscaled
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; CHECK: ldur {{w[0-9]+}}, [x0, #-256]
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%ptr_random = getelementptr i32* %p, i32 297984 ; 0x123000/4 (i.e. ADD imm)
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%val_random = load atomic i32* %ptr_random unordered, align 4
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%tot3 = add i32 %tot2, %val_random
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; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
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; CHECK: ldr {{w[0-9]+}}, [x[[ADDR]]]
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ret i32 %tot3
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}
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define i64 @atomic_load_relaxed_64(i64* %p, i32 %off32) {
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; CHECK-LABEL: atomic_load_relaxed_64:
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%ptr_unsigned = getelementptr i64* %p, i32 4095
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%val_unsigned = load atomic i64* %ptr_unsigned monotonic, align 8
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; CHECK: ldr {{x[0-9]+}}, [x0, #32760]
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%ptr_regoff = getelementptr i64* %p, i32 %off32
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%val_regoff = load atomic i64* %ptr_regoff unordered, align 8
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%tot1 = add i64 %val_unsigned, %val_regoff
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; CHECK: ldr {{x[0-9]+}}, [x0, w1, sxtw #3]
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%ptr_unscaled = getelementptr i64* %p, i32 -32
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%val_unscaled = load atomic i64* %ptr_unscaled monotonic, align 8
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%tot2 = add i64 %tot1, %val_unscaled
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; CHECK: ldur {{x[0-9]+}}, [x0, #-256]
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%ptr_random = getelementptr i64* %p, i32 148992 ; 0x123000/8 (i.e. ADD imm)
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%val_random = load atomic i64* %ptr_random unordered, align 8
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%tot3 = add i64 %tot2, %val_random
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; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
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; CHECK: ldr {{x[0-9]+}}, [x[[ADDR]]]
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ret i64 %tot3
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}
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define void @atomc_store(i32* %p) {
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store atomic i32 4, i32* %p seq_cst, align 4
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ret void
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; CHECK-LABEL: atomc_store:
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; CHECK: stlr
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}
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define void @atomic_store_relaxed_8(i8* %p, i32 %off32, i8 %val) {
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; CHECK-LABEL: atomic_store_relaxed_8:
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%ptr_unsigned = getelementptr i8* %p, i32 4095
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store atomic i8 %val, i8* %ptr_unsigned monotonic, align 1
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; CHECK: strb {{w[0-9]+}}, [x0, #4095]
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%ptr_regoff = getelementptr i8* %p, i32 %off32
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store atomic i8 %val, i8* %ptr_regoff unordered, align 1
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; CHECK: strb {{w[0-9]+}}, [x0, w1, sxtw]
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%ptr_unscaled = getelementptr i8* %p, i32 -256
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store atomic i8 %val, i8* %ptr_unscaled monotonic, align 1
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; CHECK: sturb {{w[0-9]+}}, [x0, #-256]
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%ptr_random = getelementptr i8* %p, i32 1191936 ; 0x123000 (i.e. ADD imm)
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store atomic i8 %val, i8* %ptr_random unordered, align 1
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; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
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; CHECK: strb {{w[0-9]+}}, [x[[ADDR]]]
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ret void
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}
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define void @atomic_store_relaxed_16(i16* %p, i32 %off32, i16 %val) {
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; CHECK-LABEL: atomic_store_relaxed_16:
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%ptr_unsigned = getelementptr i16* %p, i32 4095
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store atomic i16 %val, i16* %ptr_unsigned monotonic, align 2
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; CHECK: strh {{w[0-9]+}}, [x0, #8190]
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%ptr_regoff = getelementptr i16* %p, i32 %off32
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store atomic i16 %val, i16* %ptr_regoff unordered, align 2
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; CHECK: strh {{w[0-9]+}}, [x0, w1, sxtw #1]
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%ptr_unscaled = getelementptr i16* %p, i32 -128
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store atomic i16 %val, i16* %ptr_unscaled monotonic, align 2
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; CHECK: sturh {{w[0-9]+}}, [x0, #-256]
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%ptr_random = getelementptr i16* %p, i32 595968 ; 0x123000/2 (i.e. ADD imm)
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store atomic i16 %val, i16* %ptr_random unordered, align 2
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; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
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; CHECK: strh {{w[0-9]+}}, [x[[ADDR]]]
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ret void
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}
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define void @atomic_store_relaxed_32(i32* %p, i32 %off32, i32 %val) {
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; CHECK-LABEL: atomic_store_relaxed_32:
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%ptr_unsigned = getelementptr i32* %p, i32 4095
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store atomic i32 %val, i32* %ptr_unsigned monotonic, align 4
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; CHECK: str {{w[0-9]+}}, [x0, #16380]
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%ptr_regoff = getelementptr i32* %p, i32 %off32
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store atomic i32 %val, i32* %ptr_regoff unordered, align 4
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; CHECK: str {{w[0-9]+}}, [x0, w1, sxtw #2]
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%ptr_unscaled = getelementptr i32* %p, i32 -64
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store atomic i32 %val, i32* %ptr_unscaled monotonic, align 4
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; CHECK: stur {{w[0-9]+}}, [x0, #-256]
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%ptr_random = getelementptr i32* %p, i32 297984 ; 0x123000/4 (i.e. ADD imm)
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store atomic i32 %val, i32* %ptr_random unordered, align 4
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; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
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; CHECK: str {{w[0-9]+}}, [x[[ADDR]]]
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ret void
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}
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define void @atomic_store_relaxed_64(i64* %p, i32 %off32, i64 %val) {
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; CHECK-LABEL: atomic_store_relaxed_64:
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%ptr_unsigned = getelementptr i64* %p, i32 4095
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store atomic i64 %val, i64* %ptr_unsigned monotonic, align 8
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; CHECK: str {{x[0-9]+}}, [x0, #32760]
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%ptr_regoff = getelementptr i64* %p, i32 %off32
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store atomic i64 %val, i64* %ptr_regoff unordered, align 8
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; CHECK: str {{x[0-9]+}}, [x0, w1, sxtw #3]
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%ptr_unscaled = getelementptr i64* %p, i32 -32
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store atomic i64 %val, i64* %ptr_unscaled monotonic, align 8
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; CHECK: stur {{x[0-9]+}}, [x0, #-256]
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%ptr_random = getelementptr i64* %p, i32 148992 ; 0x123000/8 (i.e. ADD imm)
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store atomic i64 %val, i64* %ptr_random unordered, align 8
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; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
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; CHECK: str {{x[0-9]+}}, [x[[ADDR]]]
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ret void
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}
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; rdar://11531169
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; rdar://11531308
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%"class.X::Atomic" = type { %struct.x_atomic_t }
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%struct.x_atomic_t = type { i32 }
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@counter = external hidden global %"class.X::Atomic", align 4
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define i32 @next_id() nounwind optsize ssp align 2 {
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entry:
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%0 = atomicrmw add i32* getelementptr inbounds (%"class.X::Atomic"* @counter, i64 0, i32 0, i32 0), i32 1 seq_cst
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%add.i = add i32 %0, 1
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%tobool = icmp eq i32 %add.i, 0
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br i1 %tobool, label %if.else, label %return
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if.else: ; preds = %entry
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%1 = atomicrmw add i32* getelementptr inbounds (%"class.X::Atomic"* @counter, i64 0, i32 0, i32 0), i32 1 seq_cst
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%add.i2 = add i32 %1, 1
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br label %return
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return: ; preds = %if.else, %entry
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%retval.0 = phi i32 [ %add.i2, %if.else ], [ %add.i, %entry ]
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ret i32 %retval.0
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}
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