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ca0f4dc4f0
This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. llvm-svn: 209577
59 lines
1.5 KiB
LLVM
59 lines
1.5 KiB
LLVM
; RUN: llc -aarch64-extr-generation=true -verify-machineinstrs < %s \
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; RUN: -march=arm64 | FileCheck %s
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define i64 @ror_i64(i64 %in) {
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; CHECK-LABEL: ror_i64:
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%left = shl i64 %in, 19
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%right = lshr i64 %in, 45
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%val5 = or i64 %left, %right
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; CHECK: ror {{x[0-9]+}}, x0, #45
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ret i64 %val5
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}
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define i32 @ror_i32(i32 %in) {
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; CHECK-LABEL: ror_i32:
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%left = shl i32 %in, 9
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%right = lshr i32 %in, 23
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%val5 = or i32 %left, %right
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; CHECK: ror {{w[0-9]+}}, w0, #23
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ret i32 %val5
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}
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define i32 @extr_i32(i32 %lhs, i32 %rhs) {
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; CHECK-LABEL: extr_i32:
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%left = shl i32 %lhs, 6
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%right = lshr i32 %rhs, 26
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%val = or i32 %left, %right
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; Order of lhs and rhs matters here. Regalloc would have to be very odd to use
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; something other than w0 and w1.
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; CHECK: extr {{w[0-9]+}}, w0, w1, #26
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ret i32 %val
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}
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define i64 @extr_i64(i64 %lhs, i64 %rhs) {
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; CHECK-LABEL: extr_i64:
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%right = lshr i64 %rhs, 40
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%left = shl i64 %lhs, 24
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%val = or i64 %right, %left
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; Order of lhs and rhs matters here. Regalloc would have to be very odd to use
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; something other than w0 and w1.
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; CHECK: extr {{x[0-9]+}}, x0, x1, #40
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ret i64 %val
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}
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; Regression test: a bad experimental pattern crept into git which optimised
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; this pattern to a single EXTR.
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define i32 @extr_regress(i32 %a, i32 %b) {
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; CHECK-LABEL: extr_regress:
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%sh1 = shl i32 %a, 14
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%sh2 = lshr i32 %b, 14
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%val = or i32 %sh2, %sh1
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; CHECK-NOT: extr {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, #{{[0-9]+}}
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ret i32 %val
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; CHECK: ret
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}
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