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ca0f4dc4f0
This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. llvm-svn: 209577
50 lines
2.1 KiB
LLVM
50 lines
2.1 KiB
LLVM
; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
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define <2 x float> @cvtf32fxpu(<2 x i32> %a) nounwind readnone ssp {
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; CHECK-LABEL: cvtf32fxpu:
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; CHECK: ucvtf.2s v0, v0, #9
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; CHECK: ret
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%vcvt_n1 = tail call <2 x float> @llvm.aarch64.neon.vcvtfxu2fp.v2f32.v2i32(<2 x i32> %a, i32 9)
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ret <2 x float> %vcvt_n1
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}
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define <2 x float> @cvtf32fxps(<2 x i32> %a) nounwind readnone ssp {
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; CHECK-LABEL: cvtf32fxps:
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; CHECK: scvtf.2s v0, v0, #12
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; CHECK: ret
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%vcvt_n1 = tail call <2 x float> @llvm.aarch64.neon.vcvtfxs2fp.v2f32.v2i32(<2 x i32> %a, i32 12)
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ret <2 x float> %vcvt_n1
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}
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define <4 x float> @cvtqf32fxpu(<4 x i32> %a) nounwind readnone ssp {
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; CHECK-LABEL: cvtqf32fxpu:
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; CHECK: ucvtf.4s v0, v0, #18
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; CHECK: ret
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%vcvt_n1 = tail call <4 x float> @llvm.aarch64.neon.vcvtfxu2fp.v4f32.v4i32(<4 x i32> %a, i32 18)
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ret <4 x float> %vcvt_n1
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}
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define <4 x float> @cvtqf32fxps(<4 x i32> %a) nounwind readnone ssp {
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; CHECK-LABEL: cvtqf32fxps:
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; CHECK: scvtf.4s v0, v0, #30
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; CHECK: ret
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%vcvt_n1 = tail call <4 x float> @llvm.aarch64.neon.vcvtfxs2fp.v4f32.v4i32(<4 x i32> %a, i32 30)
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ret <4 x float> %vcvt_n1
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}
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define <2 x double> @f1(<2 x i64> %a) nounwind readnone ssp {
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%vcvt_n1 = tail call <2 x double> @llvm.aarch64.neon.vcvtfxu2fp.v2f64.v2i64(<2 x i64> %a, i32 12)
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ret <2 x double> %vcvt_n1
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}
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define <2 x double> @f2(<2 x i64> %a) nounwind readnone ssp {
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%vcvt_n1 = tail call <2 x double> @llvm.aarch64.neon.vcvtfxs2fp.v2f64.v2i64(<2 x i64> %a, i32 9)
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ret <2 x double> %vcvt_n1
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}
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declare <4 x float> @llvm.aarch64.neon.vcvtfxu2fp.v4f32.v4i32(<4 x i32>, i32) nounwind readnone
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declare <4 x float> @llvm.aarch64.neon.vcvtfxs2fp.v4f32.v4i32(<4 x i32>, i32) nounwind readnone
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declare <2 x float> @llvm.aarch64.neon.vcvtfxu2fp.v2f32.v2i32(<2 x i32>, i32) nounwind readnone
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declare <2 x float> @llvm.aarch64.neon.vcvtfxs2fp.v2f32.v2i32(<2 x i32>, i32) nounwind readnone
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declare <2 x double> @llvm.aarch64.neon.vcvtfxu2fp.v2f64.v2i64(<2 x i64>, i32) nounwind readnone
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declare <2 x double> @llvm.aarch64.neon.vcvtfxs2fp.v2f64.v2i64(<2 x i64>, i32) nounwind readnone
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