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https://github.com/RPCS3/llvm-mirror.git
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ca0f4dc4f0
This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. llvm-svn: 209577
135 lines
3.8 KiB
LLVM
135 lines
3.8 KiB
LLVM
; RUN: llc < %s -march=arm64 -aarch64-neon-syntax=apple | FileCheck %s
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define <8 x i8> @v_orrimm(<8 x i8>* %A) nounwind {
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; CHECK-LABEL: v_orrimm:
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; CHECK-NOT: mov
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; CHECK-NOT: mvn
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; CHECK: orr
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%tmp1 = load <8 x i8>* %A
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%tmp3 = or <8 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1>
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ret <8 x i8> %tmp3
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}
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define <16 x i8> @v_orrimmQ(<16 x i8>* %A) nounwind {
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; CHECK: v_orrimmQ
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; CHECK-NOT: mov
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; CHECK-NOT: mvn
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; CHECK: orr
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%tmp1 = load <16 x i8>* %A
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%tmp3 = or <16 x i8> %tmp1, <i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1, i8 0, i8 0, i8 0, i8 1>
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ret <16 x i8> %tmp3
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}
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define <8 x i8> @v_bicimm(<8 x i8>* %A) nounwind {
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; CHECK-LABEL: v_bicimm:
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; CHECK-NOT: mov
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; CHECK-NOT: mvn
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; CHECK: bic
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%tmp1 = load <8 x i8>* %A
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%tmp3 = and <8 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0 >
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ret <8 x i8> %tmp3
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}
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define <16 x i8> @v_bicimmQ(<16 x i8>* %A) nounwind {
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; CHECK-LABEL: v_bicimmQ:
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; CHECK-NOT: mov
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; CHECK-NOT: mvn
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; CHECK: bic
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%tmp1 = load <16 x i8>* %A
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%tmp3 = and <16 x i8> %tmp1, < i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0 >
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ret <16 x i8> %tmp3
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}
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define <2 x double> @foo(<2 x double> %bar) nounwind {
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; CHECK: foo
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; CHECK: fmov.2d v1, #1.0000000
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%add = fadd <2 x double> %bar, <double 1.0, double 1.0>
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ret <2 x double> %add
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}
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define <4 x i32> @movi_4s_imm_t1() nounwind readnone ssp {
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entry:
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; CHECK-LABEL: movi_4s_imm_t1:
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; CHECK: movi.4s v0, #0x4b
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ret <4 x i32> <i32 75, i32 75, i32 75, i32 75>
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}
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define <4 x i32> @movi_4s_imm_t2() nounwind readnone ssp {
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entry:
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; CHECK-LABEL: movi_4s_imm_t2:
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; CHECK: movi.4s v0, #0x4b, lsl #8
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ret <4 x i32> <i32 19200, i32 19200, i32 19200, i32 19200>
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}
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define <4 x i32> @movi_4s_imm_t3() nounwind readnone ssp {
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entry:
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; CHECK-LABEL: movi_4s_imm_t3:
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; CHECK: movi.4s v0, #0x4b, lsl #16
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ret <4 x i32> <i32 4915200, i32 4915200, i32 4915200, i32 4915200>
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}
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define <4 x i32> @movi_4s_imm_t4() nounwind readnone ssp {
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entry:
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; CHECK-LABEL: movi_4s_imm_t4:
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; CHECK: movi.4s v0, #0x4b, lsl #24
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ret <4 x i32> <i32 1258291200, i32 1258291200, i32 1258291200, i32 1258291200>
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}
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define <8 x i16> @movi_8h_imm_t5() nounwind readnone ssp {
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entry:
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; CHECK-LABEL: movi_8h_imm_t5:
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; CHECK: movi.8h v0, #0x4b
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ret <8 x i16> <i16 75, i16 75, i16 75, i16 75, i16 75, i16 75, i16 75, i16 75>
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}
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; rdar://11989841
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define <8 x i16> @movi_8h_imm_t6() nounwind readnone ssp {
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entry:
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; CHECK-LABEL: movi_8h_imm_t6:
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; CHECK: movi.8h v0, #0x4b, lsl #8
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ret <8 x i16> <i16 19200, i16 19200, i16 19200, i16 19200, i16 19200, i16 19200, i16 19200, i16 19200>
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}
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define <4 x i32> @movi_4s_imm_t7() nounwind readnone ssp {
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entry:
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; CHECK-LABEL: movi_4s_imm_t7:
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; CHECK: movi.4s v0, #0x4b, msl #8
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ret <4 x i32> <i32 19455, i32 19455, i32 19455, i32 19455>
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}
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define <4 x i32> @movi_4s_imm_t8() nounwind readnone ssp {
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entry:
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; CHECK-LABEL: movi_4s_imm_t8:
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; CHECK: movi.4s v0, #0x4b, msl #16
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ret <4 x i32> <i32 4980735, i32 4980735, i32 4980735, i32 4980735>
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}
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define <16 x i8> @movi_16b_imm_t9() nounwind readnone ssp {
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entry:
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; CHECK-LABEL: movi_16b_imm_t9:
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; CHECK: movi.16b v0, #0x4b
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ret <16 x i8> <i8 75, i8 75, i8 75, i8 75, i8 75, i8 75, i8 75, i8 75,
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i8 75, i8 75, i8 75, i8 75, i8 75, i8 75, i8 75, i8 75>
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}
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define <2 x i64> @movi_2d_imm_t10() nounwind readnone ssp {
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entry:
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; CHECK-LABEL: movi_2d_imm_t10:
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; CHECK: movi.2d v0, #0xff00ff00ff00ff
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ret <2 x i64> <i64 71777214294589695, i64 71777214294589695>
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}
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define <4 x i32> @movi_4s_imm_t11() nounwind readnone ssp {
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entry:
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; CHECK-LABEL: movi_4s_imm_t11:
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; CHECK: fmov.4s v0, #-0.32812500
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ret <4 x i32> <i32 3198681088, i32 3198681088, i32 3198681088, i32 3198681088>
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}
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define <2 x i64> @movi_2d_imm_t12() nounwind readnone ssp {
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entry:
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; CHECK-LABEL: movi_2d_imm_t12:
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; CHECK: fmov.2d v0, #-0.17187500
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ret <2 x i64> <i64 13818732506632945664, i64 13818732506632945664>
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}
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