mirror of
https://github.com/RPCS3/llvm-mirror.git
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ca0f4dc4f0
This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. llvm-svn: 209577
261 lines
7.6 KiB
LLVM
261 lines
7.6 KiB
LLVM
; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK
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define <8 x i8> @movi8b() {
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; CHECK-LABEL: movi8b:
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; CHECK: movi {{v[0-9]+}}.8b, #{{0x8|8}}
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ret <8 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
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}
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define <16 x i8> @movi16b() {
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; CHECK-LABEL: movi16b:
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; CHECK: movi {{v[0-9]+}}.16b, #{{0x8|8}}
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ret <16 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
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}
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define <2 x i32> @movi2s_lsl0() {
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; CHECK-LABEL: movi2s_lsl0:
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; CHECK: movi {{d[0-9]+}}, #0x0000ff000000ff
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ret <2 x i32> < i32 255, i32 255 >
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}
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define <2 x i32> @movi2s_lsl8() {
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; CHECK-LABEL: movi2s_lsl8:
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; CHECK: movi {{d[0-9]+}}, #0x00ff000000ff00
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ret <2 x i32> < i32 65280, i32 65280 >
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}
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define <2 x i32> @movi2s_lsl16() {
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; CHECK-LABEL: movi2s_lsl16:
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; CHECK: movi {{d[0-9]+}}, #0xff000000ff0000
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ret <2 x i32> < i32 16711680, i32 16711680 >
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}
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define <2 x i32> @movi2s_lsl24() {
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; CHECK-LABEL: movi2s_lsl24:
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; CHECK: movi {{d[0-9]+}}, #0xff000000ff000000
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ret <2 x i32> < i32 4278190080, i32 4278190080 >
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}
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define <4 x i32> @movi4s_lsl0() {
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; CHECK-LABEL: movi4s_lsl0:
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; CHECK: movi {{v[0-9]+}}.2d, #0x0000ff000000ff
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ret <4 x i32> < i32 255, i32 255, i32 255, i32 255 >
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}
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define <4 x i32> @movi4s_lsl8() {
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; CHECK-LABEL: movi4s_lsl8:
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; CHECK: movi {{v[0-9]+}}.2d, #0x00ff000000ff00
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ret <4 x i32> < i32 65280, i32 65280, i32 65280, i32 65280 >
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}
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define <4 x i32> @movi4s_lsl16() {
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; CHECK-LABEL: movi4s_lsl16:
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; CHECK: movi {{v[0-9]+}}.2d, #0xff000000ff0000
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ret <4 x i32> < i32 16711680, i32 16711680, i32 16711680, i32 16711680 >
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}
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define <4 x i32> @movi4s_lsl24() {
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; CHECK-LABEL: movi4s_lsl24:
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; CHECK: movi {{v[0-9]+}}.2d, #0xff000000ff000000
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ret <4 x i32> < i32 4278190080, i32 4278190080, i32 4278190080, i32 4278190080 >
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}
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define <4 x i16> @movi4h_lsl0() {
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; CHECK-LABEL: movi4h_lsl0:
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; CHECK: movi {{d[0-9]+}}, #0xff00ff00ff00ff
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ret <4 x i16> < i16 255, i16 255, i16 255, i16 255 >
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}
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define <4 x i16> @movi4h_lsl8() {
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; CHECK-LABEL: movi4h_lsl8:
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; CHECK: movi d0, #0xff00ff00ff00ff00
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ret <4 x i16> < i16 65280, i16 65280, i16 65280, i16 65280 >
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}
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define <8 x i16> @movi8h_lsl0() {
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; CHECK-LABEL: movi8h_lsl0:
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; CHECK: movi v0.2d, #0xff00ff00ff00ff
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ret <8 x i16> < i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255 >
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}
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define <8 x i16> @movi8h_lsl8() {
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; CHECK-LABEL: movi8h_lsl8:
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; CHECK: movi v0.2d, #0xff00ff00ff00ff00
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ret <8 x i16> < i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280 >
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}
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define <2 x i32> @mvni2s_lsl0() {
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; CHECK-LABEL: mvni2s_lsl0:
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; CHECK: mvni {{v[0-9]+}}.2s, #{{0x10|16}}
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ret <2 x i32> < i32 4294967279, i32 4294967279 >
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}
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define <2 x i32> @mvni2s_lsl8() {
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; CHECK-LABEL: mvni2s_lsl8:
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; CHECK: mvni {{v[0-9]+}}.2s, #{{0x10|16}}, lsl #8
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ret <2 x i32> < i32 4294963199, i32 4294963199 >
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}
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define <2 x i32> @mvni2s_lsl16() {
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; CHECK-LABEL: mvni2s_lsl16:
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; CHECK: mvni {{v[0-9]+}}.2s, #{{0x10|16}}, lsl #16
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ret <2 x i32> < i32 4293918719, i32 4293918719 >
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}
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define <2 x i32> @mvni2s_lsl24() {
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; CHECK-LABEL: mvni2s_lsl24:
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; CHECK: mvni {{v[0-9]+}}.2s, #{{0x10|16}}, lsl #24
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ret <2 x i32> < i32 4026531839, i32 4026531839 >
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}
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define <4 x i32> @mvni4s_lsl0() {
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; CHECK-LABEL: mvni4s_lsl0:
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; CHECK: mvni {{v[0-9]+}}.4s, #{{0x10|16}}
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ret <4 x i32> < i32 4294967279, i32 4294967279, i32 4294967279, i32 4294967279 >
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}
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define <4 x i32> @mvni4s_lsl8() {
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; CHECK-LABEL: mvni4s_lsl8:
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; CHECK: mvni {{v[0-9]+}}.4s, #{{0x10|16}}, lsl #8
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ret <4 x i32> < i32 4294963199, i32 4294963199, i32 4294963199, i32 4294963199 >
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}
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define <4 x i32> @mvni4s_lsl16() {
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; CHECK-LABEL: mvni4s_lsl16:
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; CHECK: mvni {{v[0-9]+}}.4s, #{{0x10|16}}, lsl #16
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ret <4 x i32> < i32 4293918719, i32 4293918719, i32 4293918719, i32 4293918719 >
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}
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define <4 x i32> @mvni4s_lsl24() {
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; CHECK-LABEL: mvni4s_lsl24:
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; CHECK: mvni {{v[0-9]+}}.4s, #{{0x10|16}}, lsl #24
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ret <4 x i32> < i32 4026531839, i32 4026531839, i32 4026531839, i32 4026531839 >
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}
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define <4 x i16> @mvni4h_lsl0() {
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; CHECK-LABEL: mvni4h_lsl0:
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; CHECK: mvni {{v[0-9]+}}.4h, #{{0x10|16}}
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ret <4 x i16> < i16 65519, i16 65519, i16 65519, i16 65519 >
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}
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define <4 x i16> @mvni4h_lsl8() {
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; CHECK-LABEL: mvni4h_lsl8:
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; CHECK: mvni {{v[0-9]+}}.4h, #{{0x10|16}}, lsl #8
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ret <4 x i16> < i16 61439, i16 61439, i16 61439, i16 61439 >
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}
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define <8 x i16> @mvni8h_lsl0() {
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; CHECK-LABEL: mvni8h_lsl0:
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; CHECK: mvni {{v[0-9]+}}.8h, #{{0x10|16}}
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ret <8 x i16> < i16 65519, i16 65519, i16 65519, i16 65519, i16 65519, i16 65519, i16 65519, i16 65519 >
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}
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define <8 x i16> @mvni8h_lsl8() {
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; CHECK-LABEL: mvni8h_lsl8:
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; CHECK: mvni {{v[0-9]+}}.8h, #{{0x10|16}}, lsl #8
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ret <8 x i16> < i16 61439, i16 61439, i16 61439, i16 61439, i16 61439, i16 61439, i16 61439, i16 61439 >
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}
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define <2 x i32> @movi2s_msl8(<2 x i32> %a) {
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; CHECK-LABEL: movi2s_msl8:
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; CHECK: movi {{d[0-9]+}}, #0x00ffff0000ffff
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ret <2 x i32> < i32 65535, i32 65535 >
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}
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define <2 x i32> @movi2s_msl16() {
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; CHECK-LABEL: movi2s_msl16:
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; CHECK: movi d0, #0xffffff00ffffff
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ret <2 x i32> < i32 16777215, i32 16777215 >
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}
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define <4 x i32> @movi4s_msl8() {
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; CHECK-LABEL: movi4s_msl8:
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; CHECK: movi v0.2d, #0x00ffff0000ffff
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ret <4 x i32> < i32 65535, i32 65535, i32 65535, i32 65535 >
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}
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define <4 x i32> @movi4s_msl16() {
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; CHECK-LABEL: movi4s_msl16:
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; CHECK: movi v0.2d, #0xffffff00ffffff
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ret <4 x i32> < i32 16777215, i32 16777215, i32 16777215, i32 16777215 >
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}
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define <2 x i32> @mvni2s_msl8() {
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; CHECK-LABEL: mvni2s_msl8:
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; CHECK: mvni {{v[0-9]+}}.2s, #{{0x10|16}}, msl #8
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ret <2 x i32> < i32 18446744073709547264, i32 18446744073709547264>
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}
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define <2 x i32> @mvni2s_msl16() {
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; CHECK-LABEL: mvni2s_msl16:
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; CHECK: mvni {{v[0-9]+}}.2s, #{{0x10|16}}, msl #16
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ret <2 x i32> < i32 18446744073708437504, i32 18446744073708437504>
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}
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define <4 x i32> @mvni4s_msl8() {
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; CHECK-LABEL: mvni4s_msl8:
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; CHECK: mvni {{v[0-9]+}}.4s, #{{0x10|16}}, msl #8
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ret <4 x i32> < i32 18446744073709547264, i32 18446744073709547264, i32 18446744073709547264, i32 18446744073709547264>
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}
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define <4 x i32> @mvni4s_msl16() {
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; CHECK-LABEL: mvni4s_msl16:
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; CHECK: mvni {{v[0-9]+}}.4s, #{{0x10|16}}, msl #16
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ret <4 x i32> < i32 18446744073708437504, i32 18446744073708437504, i32 18446744073708437504, i32 18446744073708437504>
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}
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define <2 x i64> @movi2d() {
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; CHECK-LABEL: movi2d:
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; CHECK: movi {{v[0-9]+}}.2d, #0xff0000ff0000ffff
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ret <2 x i64> < i64 18374687574888349695, i64 18374687574888349695 >
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}
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define <1 x i64> @movid() {
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; CHECK-LABEL: movid:
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; CHECK: movi {{d[0-9]+}}, #0xff0000ff0000ffff
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ret <1 x i64> < i64 18374687574888349695 >
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}
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define <2 x float> @fmov2s() {
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; CHECK-LABEL: fmov2s:
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; CHECK: fmov {{v[0-9]+}}.2s, #{{-12.00000000|-1.200000e\+01}}
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ret <2 x float> < float -1.2e1, float -1.2e1>
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}
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define <4 x float> @fmov4s() {
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; CHECK-LABEL: fmov4s:
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; CHECK: fmov {{v[0-9]+}}.4s, #{{-12.00000000|-1.200000e\+01}}
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ret <4 x float> < float -1.2e1, float -1.2e1, float -1.2e1, float -1.2e1>
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}
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define <2 x double> @fmov2d() {
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; CHECK-LABEL: fmov2d:
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; CHECK: fmov {{v[0-9]+}}.2d, #{{-12.00000000|-1.200000e\+01}}
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ret <2 x double> < double -1.2e1, double -1.2e1>
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}
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define <2 x i32> @movi1d_1() {
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; CHECK-LABEL: movi1d_1:
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; CHECK: movi d0, #0x{{0*}}ffffffff0000
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ret <2 x i32> < i32 -65536, i32 65535>
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}
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declare <2 x i32> @test_movi1d(<2 x i32>, <2 x i32>)
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define <2 x i32> @movi1d() {
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; CHECK-LABEL: movi1d:
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; CHECK: adrp {{x[0-9]+}}, .{{[A-Z0-9_]+}}
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; CHECK: ldr {{d[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:.{{[A-Z0-9_]+}}]
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; CHECK-NEXT: movi d1, #0x{{0*}}ffffffff0000
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%1 = tail call <2 x i32> @test_movi1d(<2 x i32> <i32 -2147483648, i32 2147450880>, <2 x i32> <i32 -65536, i32 65535>)
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ret <2 x i32> %1
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}
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