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ca0f4dc4f0
This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. llvm-svn: 209577
38 lines
1.1 KiB
LLVM
38 lines
1.1 KiB
LLVM
; RUN: llc -verify-machineinstrs -mtriple=arm64-apple-ios7.0 -o - %s | FileCheck %s
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; When generating DAG selection tables, TableGen used to only flag an
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; instruction as needing a chain on its own account if it had a built-in pattern
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; which used the chain. This meant that the AArch64 load/stores weren't
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; recognised and so both loads from %locvar below were coalesced into a single
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; LS8_LDR instruction (same operands other than the non-existent chain) and the
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; increment was lost at return.
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; This was obviously a Bad Thing.
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declare void @bar(i8*)
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define i64 @test_chains() {
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; CHECK-LABEL: test_chains:
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%locvar = alloca i8
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call void @bar(i8* %locvar)
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; CHECK: bl {{_?bar}}
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%inc.1 = load i8* %locvar
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%inc.2 = zext i8 %inc.1 to i64
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%inc.3 = add i64 %inc.2, 1
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%inc.4 = trunc i64 %inc.3 to i8
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store i8 %inc.4, i8* %locvar
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; CHECK: ldurb {{w[0-9]+}}, [x29, [[LOCADDR:#-?[0-9]+]]]
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; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, #1
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; CHECK: sturb {{w[0-9]+}}, [x29, [[LOCADDR]]]
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; CHECK: ldurb {{w[0-9]+}}, [x29, [[LOCADDR]]]
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%ret.1 = load i8* %locvar
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%ret.2 = zext i8 %ret.1 to i64
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ret i64 %ret.2
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; CHECK: ret
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}
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