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aed2e151eb
Summary: The Mips implementation only covers the feature bits described by the ELF e_flags so far. Mips stores additional feature bits such as MSA in the .MIPS.abiflags section. Also fixed a small bug this revealed where microMIPS wouldn't add the EF_MIPS_MICROMIPS flag when using -filetype=obj. Reviewers: echristo, rafael Subscribers: rafael, mehdi_amini, dsanders, sdardis, llvm-commits Differential Revision: http://reviews.llvm.org/D21125 llvm-svn: 272880
72 lines
1.6 KiB
ArmAsm
72 lines
1.6 KiB
ArmAsm
// This addresses bug 14456. We were not writing
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// out the addend to the gprel16 relocation. The
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// addend is stored in the instruction immediate
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// field.
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// RUN: llvm-mc -mcpu=mips32r2 -triple=mipsel-pc-linux -filetype=obj %s -o - \
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// RUN: | llvm-objdump -disassemble - | FileCheck %s
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// RUN: llvm-mc -mcpu=mips32r2 -triple=mips-pc-linux -filetype=obj %s -o - \
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// RUN: | llvm-objdump -disassemble - | FileCheck %s
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.text
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.abicalls
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.option pic0
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.section .mdebug.abi32,"",@progbits
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.file "/home/espindola/llvm/llvm/test/MC/Mips/mips_gprel16.ll"
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.text
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.globl testvar1
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.align 2
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.type testvar1,@function
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.set nomips16
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.ent testvar1
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testvar1: # @testvar1
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.frame $sp,0,$ra
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.mask 0x00000000,0
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.fmask 0x00000000,0
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.set noreorder
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.set nomacro
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.set noat
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# BB#0: # %entry
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// CHECK: lw ${{[0-9]+}}, 0($gp)
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lw $1, %gp_rel(var1)($gp)
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jr $ra
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sltu $2, $zero, $1
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.set at
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.set macro
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.set reorder
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.end testvar1
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$tmp0:
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.size testvar1, ($tmp0)-testvar1
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.globl testvar2
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.align 2
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.type testvar2,@function
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.set nomips16
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.ent testvar2
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testvar2: # @testvar2
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.frame $sp,0,$ra
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.mask 0x00000000,0
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.fmask 0x00000000,0
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.set noreorder
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.set nomacro
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.set noat
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# BB#0: # %entry
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// CHECK: lw ${{[0-9]+}}, 4($gp)
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lw $1, %gp_rel(var2)($gp)
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jr $ra
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sltu $2, $zero, $1
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.set at
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.set macro
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.set reorder
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.end testvar2
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$tmp1:
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.size testvar2, ($tmp1)-testvar2
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.type var1,@object # @var1
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.local var1
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.comm var1,4,4
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.type var2,@object # @var2
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.local var2
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.comm var2,4,4
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