mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-25 20:23:11 +01:00
4d431047f3
Summary: This patch (correctly) breaks some MSA tests by exposing the cases when SelectionDAG::getConstant() produces illegal types. These have been temporarily marked XFAIL and the XFAIL flag will be removed when SelectionDAG::getConstant() is fixed. There are three categories of failure: * Immediate instructions are not selected in one endian mode. * Immediates used in ldi.[bhwd] must be different according to endianness. (this only affects cases where the 'wrong' ldi is used to load the correct bitpattern. E.g. (bitcast:v2i64 (build_vector:v4i32 ...))) * Non-immediate instructions that rely on immediates affected by the previous two categories as part of their match pattern. For example, the bset match pattern is the vector equivalent of 'ws | (1 << wt)'. One test needed correcting to expect different output depending on whether big or little endian was in use. This test was test/CodeGen/Mips/msa/basic_operations.ll and experiences the second category of failure shown above. The little endian version of this test is named basic_operations_little.ll and will be merged back into basic_operations.ll in a follow up commit now that FileCheck supports multiple check prefixes. Reviewers: bkramer, jacksprat, dsanders Reviewed By: dsanders CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D1972 llvm-svn: 194806
91 lines
3.5 KiB
LLVM
91 lines
3.5 KiB
LLVM
; Test the MSA integer to floating point conversion intrinsics that are encoded
|
|
; with the 2RF instruction format.
|
|
|
|
; RUN: llc -march=mips -mattr=+msa,+fp64 < %s | FileCheck %s
|
|
; RUN: llc -march=mipsel -mattr=+msa,+fp64 < %s | FileCheck %s
|
|
|
|
@llvm_mips_ffint_s_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
|
|
@llvm_mips_ffint_s_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16
|
|
|
|
define void @llvm_mips_ffint_s_w_test() nounwind {
|
|
entry:
|
|
%0 = load <4 x i32>* @llvm_mips_ffint_s_w_ARG1
|
|
%1 = tail call <4 x float> @llvm.mips.ffint.s.w(<4 x i32> %0)
|
|
store <4 x float> %1, <4 x float>* @llvm_mips_ffint_s_w_RES
|
|
ret void
|
|
}
|
|
|
|
declare <4 x float> @llvm.mips.ffint.s.w(<4 x i32>) nounwind
|
|
|
|
; CHECK: llvm_mips_ffint_s_w_test:
|
|
; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_ffint_s_w_ARG1)
|
|
; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])
|
|
; CHECK-DAG: ffint_s.w [[WD:\$w[0-9]+]], [[WS]]
|
|
; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_ffint_s_w_RES)
|
|
; CHECK-DAG: st.w [[WD]], 0([[R2]])
|
|
; CHECK: .size llvm_mips_ffint_s_w_test
|
|
;
|
|
@llvm_mips_ffint_s_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
|
|
@llvm_mips_ffint_s_d_RES = global <2 x double> <double 0.000000e+00, double 0.000000e+00>, align 16
|
|
|
|
define void @llvm_mips_ffint_s_d_test() nounwind {
|
|
entry:
|
|
%0 = load <2 x i64>* @llvm_mips_ffint_s_d_ARG1
|
|
%1 = tail call <2 x double> @llvm.mips.ffint.s.d(<2 x i64> %0)
|
|
store <2 x double> %1, <2 x double>* @llvm_mips_ffint_s_d_RES
|
|
ret void
|
|
}
|
|
|
|
declare <2 x double> @llvm.mips.ffint.s.d(<2 x i64>) nounwind
|
|
|
|
; CHECK: llvm_mips_ffint_s_d_test:
|
|
; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_ffint_s_d_ARG1)
|
|
; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]])
|
|
; CHECK-DAG: ffint_s.d [[WD:\$w[0-9]+]], [[WS]]
|
|
; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_ffint_s_d_RES)
|
|
; CHECK-DAG: st.d [[WD]], 0([[R2]])
|
|
; CHECK: .size llvm_mips_ffint_s_d_test
|
|
;
|
|
@llvm_mips_ffint_u_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
|
|
@llvm_mips_ffint_u_w_RES = global <4 x float> <float 0.000000e+00, float 0.000000e+00, float 0.000000e+00, float 0.000000e+00>, align 16
|
|
|
|
define void @llvm_mips_ffint_u_w_test() nounwind {
|
|
entry:
|
|
%0 = load <4 x i32>* @llvm_mips_ffint_u_w_ARG1
|
|
%1 = tail call <4 x float> @llvm.mips.ffint.u.w(<4 x i32> %0)
|
|
store <4 x float> %1, <4 x float>* @llvm_mips_ffint_u_w_RES
|
|
ret void
|
|
}
|
|
|
|
declare <4 x float> @llvm.mips.ffint.u.w(<4 x i32>) nounwind
|
|
|
|
; CHECK: llvm_mips_ffint_u_w_test:
|
|
; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_ffint_u_w_ARG1)
|
|
; CHECK-DAG: ld.w [[WS:\$w[0-9]+]], 0([[R1]])
|
|
; CHECK-DAG: ffint_u.w [[WD:\$w[0-9]+]], [[WS]]
|
|
; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_ffint_u_w_RES)
|
|
; CHECK-DAG: st.w [[WD]], 0([[R2]])
|
|
; CHECK: .size llvm_mips_ffint_u_w_test
|
|
;
|
|
@llvm_mips_ffint_u_d_ARG1 = global <2 x i64> <i64 0, i64 1>, align 16
|
|
@llvm_mips_ffint_u_d_RES = global <2 x double> <double 0.000000e+00, double 0.000000e+00>, align 16
|
|
|
|
define void @llvm_mips_ffint_u_d_test() nounwind {
|
|
entry:
|
|
%0 = load <2 x i64>* @llvm_mips_ffint_u_d_ARG1
|
|
%1 = tail call <2 x double> @llvm.mips.ffint.u.d(<2 x i64> %0)
|
|
store <2 x double> %1, <2 x double>* @llvm_mips_ffint_u_d_RES
|
|
ret void
|
|
}
|
|
|
|
declare <2 x double> @llvm.mips.ffint.u.d(<2 x i64>) nounwind
|
|
|
|
; CHECK: llvm_mips_ffint_u_d_test:
|
|
; CHECK-DAG: lw [[R1:\$[0-9]+]], %got(llvm_mips_ffint_u_d_ARG1)
|
|
; CHECK-DAG: ld.d [[WS:\$w[0-9]+]], 0([[R1]])
|
|
; CHECK-DAG: ffint_u.d [[WD:\$w[0-9]+]], [[WS]]
|
|
; CHECK-DAG: lw [[R2:\$[0-9]+]], %got(llvm_mips_ffint_u_d_RES)
|
|
; CHECK-DAG: st.d [[WD]], 0([[R2]])
|
|
; CHECK: .size llvm_mips_ffint_u_d_test
|
|
;
|