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0d99339102
One of several parallel first steps to remove the target type of pointers,
replacing them with a single opaque pointer type.
This adds an explicit type parameter to the gep instruction so that when the
first parameter becomes an opaque pointer type, the type to gep through is
still available to the instructions.
* This doesn't modify gep operators, only instructions (operators will be
handled separately)
* Textual IR changes only. Bitcode (including upgrade) and changing the
in-memory representation will be in separate changes.
* geps of vectors are transformed as:
getelementptr <4 x float*> %x, ...
->getelementptr float, <4 x float*> %x, ...
Then, once the opaque pointer type is introduced, this will ultimately look
like:
getelementptr float, <4 x ptr> %x
with the unambiguous interpretation that it is a vector of pointers to float.
* address spaces remain on the pointer, not the type:
getelementptr float addrspace(1)* %x
->getelementptr float, float addrspace(1)* %x
Then, eventually:
getelementptr float, ptr addrspace(1) %x
Importantly, the massive amount of test case churn has been automated by
same crappy python code. I had to manually update a few test cases that
wouldn't fit the script's model (r228970,r229196,r229197,r229198). The
python script just massages stdin and writes the result to stdout, I
then wrapped that in a shell script to handle replacing files, then
using the usual find+xargs to migrate all the files.
update.py:
import fileinput
import sys
import re
ibrep = re.compile(r"(^.*?[^%\w]getelementptr inbounds )(((?:<\d* x )?)(.*?)(| addrspace\(\d\)) *\*(|>)(?:$| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$))")
normrep = re.compile( r"(^.*?[^%\w]getelementptr )(((?:<\d* x )?)(.*?)(| addrspace\(\d\)) *\*(|>)(?:$| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$))")
def conv(match, line):
if not match:
return line
line = match.groups()[0]
if len(match.groups()[5]) == 0:
line += match.groups()[2]
line += match.groups()[3]
line += ", "
line += match.groups()[1]
line += "\n"
return line
for line in sys.stdin:
if line.find("getelementptr ") == line.find("getelementptr inbounds"):
if line.find("getelementptr inbounds") != line.find("getelementptr inbounds ("):
line = conv(re.match(ibrep, line), line)
elif line.find("getelementptr ") != line.find("getelementptr ("):
line = conv(re.match(normrep, line), line)
sys.stdout.write(line)
apply.sh:
for name in "$@"
do
python3 `dirname "$0"`/update.py < "$name" > "$name.tmp" && mv "$name.tmp" "$name"
rm -f "$name.tmp"
done
The actual commands:
From llvm/src:
find test/ -name *.ll | xargs ./apply.sh
From llvm/src/tools/clang:
find test/ -name *.mm -o -name *.m -o -name *.cpp -o -name *.c | xargs -I '{}' ../../apply.sh "{}"
From llvm/src/tools/polly:
find test/ -name *.ll | xargs ./apply.sh
After that, check-all (with llvm, clang, clang-tools-extra, lld,
compiler-rt, and polly all checked out).
The extra 'rm' in the apply.sh script is due to a few files in clang's test
suite using interesting unicode stuff that my python script was throwing
exceptions on. None of those files needed to be migrated, so it seemed
sufficient to ignore those cases.
Reviewers: rafael, dexonsmith, grosser
Differential Revision: http://reviews.llvm.org/D7636
llvm-svn: 230786
166 lines
4.2 KiB
LLVM
166 lines
4.2 KiB
LLVM
; Test 128-bit addition in which the second operand is a zero-extended i32.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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; Check register additions. The XOR ensures that we don't instead zero-extend
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; %b into a register and use memory addition.
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define void @f1(i128 *%aptr, i32 %b) {
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; CHECK-LABEL: f1:
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; CHECK: slgfr {{%r[0-5]}}, %r3
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; CHECK: slbgr
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; CHECK: br %r14
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%a = load i128 *%aptr
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%xor = xor i128 %a, 127
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%bext = zext i32 %b to i128
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%sub = sub i128 %xor, %bext
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store i128 %sub, i128 *%aptr
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ret void
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}
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; Like f1, but using an "in-register" extension.
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define void @f2(i128 *%aptr, i64 %b) {
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; CHECK-LABEL: f2:
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; CHECK: slgfr {{%r[0-5]}}, %r3
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; CHECK: slbgr
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; CHECK: br %r14
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%a = load i128 *%aptr
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%xor = xor i128 %a, 127
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%trunc = trunc i64 %b to i32
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%bext = zext i32 %trunc to i128
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%sub = sub i128 %xor, %bext
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store i128 %sub, i128 *%aptr
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ret void
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}
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; Test register addition in cases where the second operand is zero extended
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; from i64 rather than i32, but is later masked to i32 range.
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define void @f3(i128 *%aptr, i64 %b) {
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; CHECK-LABEL: f3:
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; CHECK: slgfr {{%r[0-5]}}, %r3
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; CHECK: slbgr
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; CHECK: br %r14
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%a = load i128 *%aptr
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%xor = xor i128 %a, 127
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%bext = zext i64 %b to i128
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%and = and i128 %bext, 4294967295
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%sub = sub i128 %xor, %and
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store i128 %sub, i128 *%aptr
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ret void
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}
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; Test SLGF with no offset.
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define void @f4(i128 *%aptr, i32 *%bsrc) {
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; CHECK-LABEL: f4:
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; CHECK: slgf {{%r[0-5]}}, 0(%r3)
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; CHECK: slbgr
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; CHECK: br %r14
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%a = load i128 *%aptr
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%xor = xor i128 %a, 127
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%b = load i32 *%bsrc
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%bext = zext i32 %b to i128
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%sub = sub i128 %xor, %bext
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store i128 %sub, i128 *%aptr
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ret void
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}
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; Check the high end of the SLGF range.
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define void @f5(i128 *%aptr, i32 *%bsrc) {
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; CHECK-LABEL: f5:
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; CHECK: slgf {{%r[0-5]}}, 524284(%r3)
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; CHECK: slbgr
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; CHECK: br %r14
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%a = load i128 *%aptr
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%xor = xor i128 %a, 127
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%ptr = getelementptr i32, i32 *%bsrc, i64 131071
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%b = load i32 *%ptr
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%bext = zext i32 %b to i128
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%sub = sub i128 %xor, %bext
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store i128 %sub, i128 *%aptr
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ret void
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}
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; Check the next word up, which must use separate address logic.
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; Other sequences besides this one would be OK.
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define void @f6(i128 *%aptr, i32 *%bsrc) {
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; CHECK-LABEL: f6:
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; CHECK: agfi %r3, 524288
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; CHECK: slgf {{%r[0-5]}}, 0(%r3)
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; CHECK: slbgr
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; CHECK: br %r14
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%a = load i128 *%aptr
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%xor = xor i128 %a, 127
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%ptr = getelementptr i32, i32 *%bsrc, i64 131072
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%b = load i32 *%ptr
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%bext = zext i32 %b to i128
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%sub = sub i128 %xor, %bext
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store i128 %sub, i128 *%aptr
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ret void
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}
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; Check the high end of the negative aligned SLGF range.
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define void @f7(i128 *%aptr, i32 *%bsrc) {
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; CHECK-LABEL: f7:
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; CHECK: slgf {{%r[0-5]}}, -4(%r3)
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; CHECK: slbgr
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; CHECK: br %r14
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%a = load i128 *%aptr
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%xor = xor i128 %a, 127
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%ptr = getelementptr i32, i32 *%bsrc, i128 -1
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%b = load i32 *%ptr
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%bext = zext i32 %b to i128
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%sub = sub i128 %xor, %bext
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store i128 %sub, i128 *%aptr
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ret void
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}
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; Check the low end of the SLGF range.
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define void @f8(i128 *%aptr, i32 *%bsrc) {
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; CHECK-LABEL: f8:
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; CHECK: slgf {{%r[0-5]}}, -524288(%r3)
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; CHECK: slbgr
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; CHECK: br %r14
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%a = load i128 *%aptr
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%xor = xor i128 %a, 127
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%ptr = getelementptr i32, i32 *%bsrc, i128 -131072
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%b = load i32 *%ptr
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%bext = zext i32 %b to i128
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%sub = sub i128 %xor, %bext
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store i128 %sub, i128 *%aptr
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ret void
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}
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; Check the next word down, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define void @f9(i128 *%aptr, i32 *%bsrc) {
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; CHECK-LABEL: f9:
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; CHECK: agfi %r3, -524292
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; CHECK: slgf {{%r[0-5]}}, 0(%r3)
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; CHECK: slbgr
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; CHECK: br %r14
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%a = load i128 *%aptr
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%xor = xor i128 %a, 127
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%ptr = getelementptr i32, i32 *%bsrc, i128 -131073
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%b = load i32 *%ptr
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%bext = zext i32 %b to i128
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%sub = sub i128 %xor, %bext
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store i128 %sub, i128 *%aptr
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ret void
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}
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; Check that SLGF allows an index.
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define void @f10(i128 *%aptr, i64 %src, i64 %index) {
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; CHECK-LABEL: f10:
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; CHECK: slgf {{%r[0-5]}}, 524284({{%r4,%r3|%r3,%r4}})
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; CHECK: br %r14
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%a = load i128 *%aptr
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%xor = xor i128 %a, 127
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%add1 = add i64 %src, %index
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%add2 = add i64 %add1, 524284
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%ptr = inttoptr i64 %add2 to i32 *
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%b = load i32 *%ptr
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%bext = zext i32 %b to i128
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%sub = sub i128 %xor, %bext
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store i128 %sub, i128 *%aptr
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ret void
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}
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