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9d042ff7dc
Certain optimisations from ConstantHoisting and CGP rely on Selection DAG not seeing through to the constant in other blocks. Revert this patch while we come up with a better way to handle that. I will try to follow this up with some better tests. llvm-svn: 358113
154 lines
6.8 KiB
LLVM
154 lines
6.8 KiB
LLVM
;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s
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;CHECK-LABEL: {{^}}s_buffer_load_imm:
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;CHECK-NOT: s_waitcnt;
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;CHECK: s_buffer_load_dword s{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0x4
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define amdgpu_ps void @s_buffer_load_imm(<4 x i32> inreg %desc) {
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main_body:
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%load = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 4, i32 0)
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%bitcast = bitcast i32 %load to float
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call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %bitcast, float undef, float undef, float undef, i1 true, i1 true)
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ret void
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}
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;CHECK-LABEL: {{^}}s_buffer_load_index:
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;CHECK-NOT: s_waitcnt;
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;CHECK: s_buffer_load_dword s{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}}
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define amdgpu_ps void @s_buffer_load_index(<4 x i32> inreg %desc, i32 inreg %index) {
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main_body:
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%load = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 %index, i32 0)
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%bitcast = bitcast i32 %load to float
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call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %bitcast, float undef, float undef, float undef, i1 true, i1 true)
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ret void
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}
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;CHECK-LABEL: {{^}}s_buffer_loadx2_imm:
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;CHECK-NOT: s_waitcnt;
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;CHECK: s_buffer_load_dwordx2 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0x40
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define amdgpu_ps void @s_buffer_loadx2_imm(<4 x i32> inreg %desc) {
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main_body:
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%load = call <2 x i32> @llvm.amdgcn.s.buffer.load.v2i32(<4 x i32> %desc, i32 64, i32 0)
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%bitcast = bitcast <2 x i32> %load to <2 x float>
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%x = extractelement <2 x float> %bitcast, i32 0
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%y = extractelement <2 x float> %bitcast, i32 1
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call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %x, float %y, float undef, float undef, i1 true, i1 true)
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ret void
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}
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;CHECK-LABEL: {{^}}s_buffer_loadx2_index:
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;CHECK-NOT: s_waitcnt;
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;CHECK: s_buffer_load_dwordx2 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}}
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define amdgpu_ps void @s_buffer_loadx2_index(<4 x i32> inreg %desc, i32 inreg %index) {
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main_body:
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%load = call <2 x i32> @llvm.amdgcn.s.buffer.load.v2i32(<4 x i32> %desc, i32 %index, i32 0)
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%bitcast = bitcast <2 x i32> %load to <2 x float>
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%x = extractelement <2 x float> %bitcast, i32 0
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%y = extractelement <2 x float> %bitcast, i32 1
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call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %x, float %y, float undef, float undef, i1 true, i1 true)
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ret void
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}
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;CHECK-LABEL: {{^}}s_buffer_loadx4_imm:
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;CHECK-NOT: s_waitcnt;
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;CHECK: s_buffer_load_dwordx4 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0xc8
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define amdgpu_ps void @s_buffer_loadx4_imm(<4 x i32> inreg %desc) {
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main_body:
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%load = call <4 x i32> @llvm.amdgcn.s.buffer.load.v4i32(<4 x i32> %desc, i32 200, i32 0)
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%bitcast = bitcast <4 x i32> %load to <4 x float>
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%x = extractelement <4 x float> %bitcast, i32 0
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%y = extractelement <4 x float> %bitcast, i32 1
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%z = extractelement <4 x float> %bitcast, i32 2
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%w = extractelement <4 x float> %bitcast, i32 3
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call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %x, float %y, float %z, float %w, i1 true, i1 true)
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ret void
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}
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;CHECK-LABEL: {{^}}s_buffer_loadx4_index:
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;CHECK-NOT: s_waitcnt;
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;CHECK: s_buffer_load_dwordx4 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}}
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define amdgpu_ps void @s_buffer_loadx4_index(<4 x i32> inreg %desc, i32 inreg %index) {
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main_body:
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%load = call <4 x i32> @llvm.amdgcn.s.buffer.load.v4i32(<4 x i32> %desc, i32 %index, i32 0)
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%bitcast = bitcast <4 x i32> %load to <4 x float>
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%x = extractelement <4 x float> %bitcast, i32 0
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%y = extractelement <4 x float> %bitcast, i32 1
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%z = extractelement <4 x float> %bitcast, i32 2
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%w = extractelement <4 x float> %bitcast, i32 3
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call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %x, float %y, float %z, float %w, i1 true, i1 true)
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ret void
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}
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;CHECK-LABEL: {{^}}s_buffer_load_imm_mergex2:
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;CHECK-NOT: s_waitcnt;
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;CHECK: s_buffer_load_dwordx2 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0x4
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define amdgpu_ps void @s_buffer_load_imm_mergex2(<4 x i32> inreg %desc) {
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main_body:
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%load0 = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 4, i32 0)
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%load1 = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 8, i32 0)
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%x = bitcast i32 %load0 to float
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%y = bitcast i32 %load1 to float
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call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %x, float %y, float undef, float undef, i1 true, i1 true)
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ret void
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}
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;CHECK-LABEL: {{^}}s_buffer_load_imm_mergex4:
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;CHECK-NOT: s_waitcnt;
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;CHECK: s_buffer_load_dwordx4 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0x8
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define amdgpu_ps void @s_buffer_load_imm_mergex4(<4 x i32> inreg %desc) {
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main_body:
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%load0 = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 8, i32 0)
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%load1 = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 12, i32 0)
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%load2 = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 16, i32 0)
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%load3 = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 20, i32 0)
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%x = bitcast i32 %load0 to float
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%y = bitcast i32 %load1 to float
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%z = bitcast i32 %load2 to float
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%w = bitcast i32 %load3 to float
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call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %x, float %y, float %z, float %w, i1 true, i1 true)
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ret void
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}
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;CHECK-LABEL: {{^}}s_buffer_load_index_across_bb:
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;CHECK-NOT: s_waitcnt;
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;CHECK: v_or_b32
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;CHECK: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen
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define amdgpu_ps void @s_buffer_load_index_across_bb(<4 x i32> inreg %desc, i32 %index) {
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main_body:
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%tmp = shl i32 %index, 4
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br label %bb1
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bb1: ; preds = %main_body
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%tmp1 = or i32 %tmp, 8
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%load = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 %tmp1, i32 0)
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%bitcast = bitcast i32 %load to float
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call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %bitcast, float undef, float undef, float undef, i1 true, i1 true)
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ret void
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}
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;CHECK-LABEL: {{^}}s_buffer_load_index_across_bb_merged:
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;CHECK-NOT: s_waitcnt;
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;CHECK: v_or_b32
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;CHECK: v_or_b32
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;CHECK: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen
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;CHECK: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0 offen
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define amdgpu_ps void @s_buffer_load_index_across_bb_merged(<4 x i32> inreg %desc, i32 %index) {
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main_body:
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%tmp = shl i32 %index, 4
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br label %bb1
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bb1: ; preds = %main_body
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%tmp1 = or i32 %tmp, 8
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%load = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 %tmp1, i32 0)
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%tmp2 = or i32 %tmp1, 4
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%load2 = tail call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 %tmp2, i32 0)
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%bitcast = bitcast i32 %load to float
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%bitcast2 = bitcast i32 %load2 to float
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call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %bitcast, float %bitcast2, float undef, float undef, i1 true, i1 true)
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ret void
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}
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declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1)
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declare i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32>, i32, i32)
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declare <2 x i32> @llvm.amdgcn.s.buffer.load.v2i32(<4 x i32>, i32, i32)
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declare <4 x i32> @llvm.amdgcn.s.buffer.load.v4i32(<4 x i32>, i32, i32)
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