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216a9fc9a1
Summary: The symbols use the processor-specific SHN_AMDGPU_LDS section index introduced with a previous change. The linker is then expected to resolve relocations, which are also emitted. Initially disabled for HSA and PAL environments until they have caught up in terms of linker and runtime loader. Some notes: - The llvm.amdgcn.groupstaticsize intrinsics can no longer be lowered to a constant at compile times, which means some tests can no longer be applied. The current "solution" is a terrible hack, but the intrinsic isn't used by Mesa, so we can keep it for now. - We no longer know the full LDS size per kernel at compile time, which means that we can no longer generate a relevant error message at compile time. It would be possible to add a check for the size of individual variables, but ultimately the linker will have to perform the final check. Change-Id: If66dbf33fccfbf3609aefefa2558ac0850d42275 Reviewers: arsenm, rampitec, t-tye, b-sumner, jsjodin Subscribers: qcolombet, kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D61494 llvm-svn: 364297
83 lines
3.5 KiB
LLVM
83 lines
3.5 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s
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; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=GCN %s
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@local_memory.local_mem = internal unnamed_addr addrspace(3) global [128 x i32] undef, align 4
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; GCN-LABEL: {{^}}local_memory:
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; GCN-NOT: s_wqm_b64
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; GCN: ds_write_b32
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; GCN: s_barrier
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; GCN: ds_read_b32 {{v[0-9]+}},
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define amdgpu_kernel void @local_memory(i32 addrspace(1)* %out) #0 {
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entry:
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%y.i = call i32 @llvm.amdgcn.workitem.id.x() #1
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%arrayidx = getelementptr inbounds [128 x i32], [128 x i32] addrspace(3)* @local_memory.local_mem, i32 0, i32 %y.i
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store i32 %y.i, i32 addrspace(3)* %arrayidx, align 4
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%add = add nsw i32 %y.i, 1
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%cmp = icmp eq i32 %add, 16
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%.add = select i1 %cmp, i32 0, i32 %add
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call void @llvm.amdgcn.s.barrier()
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%arrayidx1 = getelementptr inbounds [128 x i32], [128 x i32] addrspace(3)* @local_memory.local_mem, i32 0, i32 %.add
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%tmp = load i32, i32 addrspace(3)* %arrayidx1, align 4
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%arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 %y.i
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store i32 %tmp, i32 addrspace(1)* %arrayidx2, align 4
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ret void
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}
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@local_memory_two_objects.local_mem0 = internal unnamed_addr addrspace(3) global [4 x i32] undef, align 4
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@local_memory_two_objects.local_mem1 = internal unnamed_addr addrspace(3) global [4 x i32] undef, align 4
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; Check that the LDS size emitted correctly
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; EG: .long 166120
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; EG-NEXT: .long 8
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; GCN: .long 47180
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; GCN-NEXT: .long 32900
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; GCN-LABEL: {{^}}local_memory_two_objects:
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; GCN: v_lshlrev_b32_e32 [[ADDRW:v[0-9]+]], 2, v0
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; CI-DAG: ds_write2_b32 [[ADDRW]], {{v[0-9]+}}, {{v[0-9]+}} offset1:4
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; SI-DAG: ds_write2_b32 [[ADDRW]], {{v[0-9]+}}, {{v[0-9]+}} offset1:4
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; GCN: s_barrier
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; SI-DAG: v_sub_i32_e32 [[SUB0:v[0-9]+]], vcc, 28, [[ADDRW]]
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; SI-DAG: v_sub_i32_e32 [[SUB1:v[0-9]+]], vcc, 12, [[ADDRW]]
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; SI-DAG: ds_read_b32 v{{[0-9]+}}, [[SUB0]]
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; SI-DAG: ds_read_b32 v{{[0-9]+}}, [[SUB1]]
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; CI: v_sub_i32_e32 [[SUB:v[0-9]+]], vcc, 0, [[ADDRW]]
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; CI: ds_read2_b32 {{v\[[0-9]+:[0-9]+\]}}, [[SUB]] offset0:3 offset1:7
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define amdgpu_kernel void @local_memory_two_objects(i32 addrspace(1)* %out) #0 {
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entry:
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%x.i = call i32 @llvm.amdgcn.workitem.id.x()
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%arrayidx = getelementptr inbounds [4 x i32], [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem0, i32 0, i32 %x.i
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store i32 %x.i, i32 addrspace(3)* %arrayidx, align 4
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%mul = shl nsw i32 %x.i, 1
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%arrayidx1 = getelementptr inbounds [4 x i32], [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem1, i32 0, i32 %x.i
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store i32 %mul, i32 addrspace(3)* %arrayidx1, align 4
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%sub = sub nsw i32 3, %x.i
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call void @llvm.amdgcn.s.barrier()
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%arrayidx2 = getelementptr inbounds [4 x i32], [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem0, i32 0, i32 %sub
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%tmp = load i32, i32 addrspace(3)* %arrayidx2, align 4
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%arrayidx3 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 %x.i
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store i32 %tmp, i32 addrspace(1)* %arrayidx3, align 4
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%arrayidx4 = getelementptr inbounds [4 x i32], [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem1, i32 0, i32 %sub
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%tmp1 = load i32, i32 addrspace(3)* %arrayidx4, align 4
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%add = add nsw i32 %x.i, 4
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%arrayidx5 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 %add
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store i32 %tmp1, i32 addrspace(1)* %arrayidx5, align 4
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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declare void @llvm.amdgcn.s.barrier() #2
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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attributes #2 = { convergent nounwind }
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