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1d5f4c66da
This patch series adds support for the next-generation arch13 CPU architecture to the SystemZ backend. This includes: - Basic support for the new processor and its features. - Assembler/disassembler support for new instructions. - CodeGen for new instructions, including new LLVM intrinsics. - Scheduler description for the new processor. - Detection of arch13 as host processor. Note: No currently available Z system supports the arch13 architecture. Once new systems become available, the official system name will be added as supported -march name. llvm-svn: 365932
41 lines
1.1 KiB
LLVM
41 lines
1.1 KiB
LLVM
; Test conversions between integer and float elements on arch13.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch13 | FileCheck %s
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; Test conversion of f32s to signed i32s.
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define <4 x i32> @f1(<4 x float> %floats) {
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; CHECK-LABEL: f1:
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; CHECK: vcfeb %v24, %v24, 0, 5
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; CHECK: br %r14
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%dwords = fptosi <4 x float> %floats to <4 x i32>
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ret <4 x i32> %dwords
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}
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; Test conversion of f32s to unsigned i32s.
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define <4 x i32> @f2(<4 x float> %floats) {
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; CHECK-LABEL: f2:
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; CHECK: vclfeb %v24, %v24, 0, 5
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; CHECK: br %r14
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%dwords = fptoui <4 x float> %floats to <4 x i32>
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ret <4 x i32> %dwords
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}
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; Test conversion of signed i32s to f32s.
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define <4 x float> @f3(<4 x i32> %dwords) {
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; CHECK-LABEL: f3:
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; CHECK: vcefb %v24, %v24, 0, 0
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; CHECK: br %r14
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%floats = sitofp <4 x i32> %dwords to <4 x float>
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ret <4 x float> %floats
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}
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; Test conversion of unsigned i32s to f32s.
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define <4 x float> @f4(<4 x i32> %dwords) {
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; CHECK-LABEL: f4:
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; CHECK: vcelfb %v24, %v24, 0, 0
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; CHECK: br %r14
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%floats = uitofp <4 x i32> %dwords to <4 x float>
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ret <4 x float> %floats
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}
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