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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-26 04:32:44 +01:00
llvm-mirror/docs/CommandGuide
Andrea Di Biagio 7e5d9331c7 [llvm-mca] Report the number of dispatched micro opcodes in the DispatchStatistics view.
This patch introduces the following changes to the DispatchStatistics view:
 * DispatchStatistics now reports the number of dispatched opcodes instead of
   the number of dispatched instructions.
 * The "Dynamic Dispatch Stall Cycles" table now also reports the percentage of
   stall cycles against the total simulated cycles.

This change allows users to easily compare dispatch group sizes with the
processor DispatchWidth.
Before this change, it was difficult to correlate the two numbers, since
DispatchStatistics view reported numbers of instructions (instead of opcodes).
DispatchWidth defines the maximum size of a dispatch group in terms of number of
micro opcodes.

The other change introduced by this patch is related to how DispatchStage
generates "instruction dispatch" events.
In particular:
 * There can be multiple dispatch events associated with a same instruction
 * Each dispatch event now encapsulates the number of dispatched micro opcodes.

The number of micro opcodes declared by an instruction may exceed the processor
DispatchWidth. Therefore, we cannot assume that instructions are always fully
dispatched in a single cycle.
DispatchStage knows already how to handle instructions declaring a number of
opcodes bigger that DispatchWidth. However, DispatchStage always emitted a
single instruction dispatch event (during the first simulated dispatch cycle)
for instructions dispatched.

With this patch, DispatchStage now correctly notifies multiple dispatch events
for instructions that cannot be dispatched in a single cycle.

A few views had to be modified. Views can no longer assume that there can only
be one dispatch event per instruction.

Tests (and docs) have been updated.

Differential Revision: https://reviews.llvm.org/D51430

llvm-svn: 341055
2018-08-30 10:50:20 +00:00
..
bugpoint.rst
dsymutil.rst [dsymutil] Upstream emitting of papertrail warnings. 2018-04-02 10:40:43 +00:00
FileCheck.rst [docs] Fix an LLVM-syntax code block to actually be valid LLVM synatx. 2018-08-06 01:41:25 +00:00
index.rst Add a CommandGuide for llvm-objdump 2018-08-08 14:39:22 +00:00
lit.rst [llvm] Document "%T" as deprecated in CommandGuide/lit.rst 2018-08-25 01:27:48 +00:00
llc.rst [MC] Fix -stack-size-section on ARM 2018-01-17 09:01:29 +00:00
lli.rst [AArch64] Add Tiny Code Model for AArch64 2018-08-22 11:31:39 +00:00
llvm-ar.rst
llvm-as.rst
llvm-bcanalyzer.rst
llvm-build.rst
llvm-config.rst
llvm-cov.rst [docs] Update usage directive for llvm-cov report -show-functions 2018-07-13 22:39:31 +00:00
llvm-diff.rst
llvm-dis.rst
llvm-dwarfdump.rst Remove duplicate option from documentation. 2017-12-09 19:09:59 +00:00
llvm-exegesis-analysis.png [llvm-exegesis] Show sched class details in analysis. 2018-05-24 10:47:05 +00:00
llvm-exegesis.rst [docs] Fix indentation of llvm-exegesis command line arguments 2018-06-18 20:05:02 +00:00
llvm-extract.rst
llvm-lib.rst
llvm-link.rst
llvm-mca.rst [llvm-mca] Report the number of dispatched micro opcodes in the DispatchStatistics view. 2018-08-30 10:50:20 +00:00
llvm-nm.rst nm: Add -no-weak flag for hiding weak symbols 2018-07-02 17:24:37 +00:00
llvm-objdump.rst Add a CommandGuide for llvm-objdump 2018-08-08 14:39:22 +00:00
llvm-pdbutil.rst
llvm-profdata.rst
llvm-readobj.rst
llvm-stress.rst
llvm-symbolizer.rst
opt.rst Rename DEBUG macro to LLVM_DEBUG. 2018-05-14 12:53:11 +00:00
tblgen.rst [TableGen] Add a general-purpose JSON backend. 2018-07-11 08:40:19 +00:00