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https://github.com/RPCS3/llvm-mirror.git
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40043ea4ca
Move instruction attributes into the `RISCVII` namespace and add associated helper functions. Differential Revision: https://reviews.llvm.org/D102268
249 lines
8.0 KiB
C++
249 lines
8.0 KiB
C++
//===-- RISCVMCInstLower.cpp - Convert RISCV MachineInstr to an MCInst ------=//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains code to lower RISCV MachineInstrs to their corresponding
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// MCInst records.
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//
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//===----------------------------------------------------------------------===//
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#include "RISCV.h"
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#include "RISCVSubtarget.h"
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#include "MCTargetDesc/RISCVMCExpr.h"
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#include "llvm/CodeGen/AsmPrinter.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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static MCOperand lowerSymbolOperand(const MachineOperand &MO, MCSymbol *Sym,
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const AsmPrinter &AP) {
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MCContext &Ctx = AP.OutContext;
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RISCVMCExpr::VariantKind Kind;
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switch (MO.getTargetFlags()) {
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default:
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llvm_unreachable("Unknown target flag on GV operand");
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case RISCVII::MO_None:
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Kind = RISCVMCExpr::VK_RISCV_None;
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break;
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case RISCVII::MO_CALL:
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Kind = RISCVMCExpr::VK_RISCV_CALL;
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break;
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case RISCVII::MO_PLT:
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Kind = RISCVMCExpr::VK_RISCV_CALL_PLT;
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break;
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case RISCVII::MO_LO:
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Kind = RISCVMCExpr::VK_RISCV_LO;
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break;
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case RISCVII::MO_HI:
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Kind = RISCVMCExpr::VK_RISCV_HI;
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break;
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case RISCVII::MO_PCREL_LO:
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Kind = RISCVMCExpr::VK_RISCV_PCREL_LO;
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break;
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case RISCVII::MO_PCREL_HI:
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Kind = RISCVMCExpr::VK_RISCV_PCREL_HI;
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break;
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case RISCVII::MO_GOT_HI:
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Kind = RISCVMCExpr::VK_RISCV_GOT_HI;
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break;
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case RISCVII::MO_TPREL_LO:
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Kind = RISCVMCExpr::VK_RISCV_TPREL_LO;
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break;
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case RISCVII::MO_TPREL_HI:
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Kind = RISCVMCExpr::VK_RISCV_TPREL_HI;
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break;
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case RISCVII::MO_TPREL_ADD:
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Kind = RISCVMCExpr::VK_RISCV_TPREL_ADD;
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break;
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case RISCVII::MO_TLS_GOT_HI:
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Kind = RISCVMCExpr::VK_RISCV_TLS_GOT_HI;
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break;
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case RISCVII::MO_TLS_GD_HI:
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Kind = RISCVMCExpr::VK_RISCV_TLS_GD_HI;
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break;
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}
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const MCExpr *ME =
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MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, Ctx);
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if (!MO.isJTI() && !MO.isMBB() && MO.getOffset())
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ME = MCBinaryExpr::createAdd(
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ME, MCConstantExpr::create(MO.getOffset(), Ctx), Ctx);
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if (Kind != RISCVMCExpr::VK_RISCV_None)
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ME = RISCVMCExpr::create(ME, Kind, Ctx);
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return MCOperand::createExpr(ME);
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}
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bool llvm::LowerRISCVMachineOperandToMCOperand(const MachineOperand &MO,
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MCOperand &MCOp,
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const AsmPrinter &AP) {
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switch (MO.getType()) {
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default:
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report_fatal_error("LowerRISCVMachineInstrToMCInst: unknown operand type");
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case MachineOperand::MO_Register:
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// Ignore all implicit register operands.
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if (MO.isImplicit())
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return false;
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MCOp = MCOperand::createReg(MO.getReg());
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break;
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case MachineOperand::MO_RegisterMask:
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// Regmasks are like implicit defs.
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return false;
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case MachineOperand::MO_Immediate:
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MCOp = MCOperand::createImm(MO.getImm());
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break;
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case MachineOperand::MO_MachineBasicBlock:
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MCOp = lowerSymbolOperand(MO, MO.getMBB()->getSymbol(), AP);
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break;
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case MachineOperand::MO_GlobalAddress:
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MCOp = lowerSymbolOperand(MO, AP.getSymbolPreferLocal(*MO.getGlobal()), AP);
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break;
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case MachineOperand::MO_BlockAddress:
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MCOp = lowerSymbolOperand(
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MO, AP.GetBlockAddressSymbol(MO.getBlockAddress()), AP);
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break;
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case MachineOperand::MO_ExternalSymbol:
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MCOp = lowerSymbolOperand(
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MO, AP.GetExternalSymbolSymbol(MO.getSymbolName()), AP);
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break;
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case MachineOperand::MO_ConstantPoolIndex:
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MCOp = lowerSymbolOperand(MO, AP.GetCPISymbol(MO.getIndex()), AP);
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break;
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case MachineOperand::MO_JumpTableIndex:
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MCOp = lowerSymbolOperand(MO, AP.GetJTISymbol(MO.getIndex()), AP);
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break;
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}
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return true;
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}
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static bool lowerRISCVVMachineInstrToMCInst(const MachineInstr *MI,
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MCInst &OutMI) {
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const RISCVVPseudosTable::PseudoInfo *RVV =
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RISCVVPseudosTable::getPseudoInfo(MI->getOpcode());
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if (!RVV)
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return false;
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OutMI.setOpcode(RVV->BaseInstr);
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const MachineBasicBlock *MBB = MI->getParent();
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assert(MBB && "MI expected to be in a basic block");
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const MachineFunction *MF = MBB->getParent();
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assert(MF && "MBB expected to be in a machine function");
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const TargetRegisterInfo *TRI =
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MF->getSubtarget<RISCVSubtarget>().getRegisterInfo();
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assert(TRI && "TargetRegisterInfo expected");
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uint64_t TSFlags = MI->getDesc().TSFlags;
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int NumOps = MI->getNumExplicitOperands();
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for (const MachineOperand &MO : MI->explicit_operands()) {
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int OpNo = (int)MI->getOperandNo(&MO);
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assert(OpNo >= 0 && "Operand number doesn't fit in an 'int' type");
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// Skip VL and SEW operands which are the last two operands if present.
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if (RISCVII::hasVLOp(TSFlags) && OpNo == (NumOps - 2))
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continue;
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if (RISCVII::hasSEWOp(TSFlags) && OpNo == (NumOps - 1))
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continue;
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// Skip merge op. It should be the first operand after the result.
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if (RISCVII::hasMergeOp(TSFlags) && OpNo == 1) {
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assert(MI->getNumExplicitDefs() == 1);
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continue;
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}
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MCOperand MCOp;
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switch (MO.getType()) {
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default:
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llvm_unreachable("Unknown operand type");
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case MachineOperand::MO_Register: {
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unsigned Reg = MO.getReg();
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if (RISCV::VRM2RegClass.contains(Reg) ||
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RISCV::VRM4RegClass.contains(Reg) ||
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RISCV::VRM8RegClass.contains(Reg)) {
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Reg = TRI->getSubReg(Reg, RISCV::sub_vrm1_0);
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assert(Reg && "Subregister does not exist");
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} else if (RISCV::FPR16RegClass.contains(Reg)) {
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Reg = TRI->getMatchingSuperReg(Reg, RISCV::sub_16, &RISCV::FPR32RegClass);
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assert(Reg && "Subregister does not exist");
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} else if (RISCV::FPR64RegClass.contains(Reg)) {
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Reg = TRI->getSubReg(Reg, RISCV::sub_32);
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assert(Reg && "Superregister does not exist");
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}
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MCOp = MCOperand::createReg(Reg);
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break;
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}
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case MachineOperand::MO_Immediate:
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MCOp = MCOperand::createImm(MO.getImm());
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break;
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}
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OutMI.addOperand(MCOp);
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}
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// Unmasked pseudo instructions need to append dummy mask operand to
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// V instructions. All V instructions are modeled as the masked version.
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if (RISCVII::hasDummyMaskOp(TSFlags))
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OutMI.addOperand(MCOperand::createReg(RISCV::NoRegister));
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return true;
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}
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bool llvm::lowerRISCVMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
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AsmPrinter &AP) {
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if (lowerRISCVVMachineInstrToMCInst(MI, OutMI))
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return false;
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OutMI.setOpcode(MI->getOpcode());
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for (const MachineOperand &MO : MI->operands()) {
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MCOperand MCOp;
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if (LowerRISCVMachineOperandToMCOperand(MO, MCOp, AP))
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OutMI.addOperand(MCOp);
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}
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switch (OutMI.getOpcode()) {
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case TargetOpcode::PATCHABLE_FUNCTION_ENTER: {
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const Function &F = MI->getParent()->getParent()->getFunction();
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if (F.hasFnAttribute("patchable-function-entry")) {
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unsigned Num;
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if (F.getFnAttribute("patchable-function-entry")
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.getValueAsString()
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.getAsInteger(10, Num))
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return false;
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AP.emitNops(Num);
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return true;
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}
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break;
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}
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case RISCV::PseudoReadVLENB:
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OutMI.setOpcode(RISCV::CSRRS);
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OutMI.addOperand(MCOperand::createImm(
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RISCVSysReg::lookupSysRegByName("VLENB")->Encoding));
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OutMI.addOperand(MCOperand::createReg(RISCV::X0));
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break;
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case RISCV::PseudoReadVL:
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OutMI.setOpcode(RISCV::CSRRS);
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OutMI.addOperand(
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MCOperand::createImm(RISCVSysReg::lookupSysRegByName("VL")->Encoding));
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OutMI.addOperand(MCOperand::createReg(RISCV::X0));
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break;
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}
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return false;
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}
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