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985d51d2a5
Fixed bugs https://bugs.llvm.org//show_bug.cgi?id=49643, https://bugs.llvm.org//show_bug.cgi?id=49644, https://bugs.llvm.org//show_bug.cgi?id=49645. Differential Revision: https://reviews.llvm.org/D99413
71 lines
3.0 KiB
LLVM
71 lines
3.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: opt -S -codegenprepare -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 < %s | FileCheck -check-prefix=OPT %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 < %s | FileCheck -check-prefix=GCN %s
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; Make sure we match the addressing mode offset of csub intrinsics across blocks.
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define amdgpu_kernel void @test_sink_small_offset_global_atomic_csub_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in) {
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; OPT-LABEL: @test_sink_small_offset_global_atomic_csub_i32(
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; OPT-NEXT: entry:
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; OPT-NEXT: [[OUT_GEP:%.*]] = getelementptr i32, i32 addrspace(1)* [[OUT:%.*]], i32 999999
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; OPT-NEXT: [[TID:%.*]] = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #3
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; OPT-NEXT: [[CMP:%.*]] = icmp eq i32 [[TID]], 0
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; OPT-NEXT: br i1 [[CMP]], label [[ENDIF:%.*]], label [[IF:%.*]]
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; OPT: if:
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; OPT-NEXT: [[TMP0:%.*]] = bitcast i32 addrspace(1)* [[IN:%.*]] to i8 addrspace(1)*
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; OPT-NEXT: [[SUNKADDR:%.*]] = getelementptr i8, i8 addrspace(1)* [[TMP0]], i64 28
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; OPT-NEXT: [[TMP1:%.*]] = bitcast i8 addrspace(1)* [[SUNKADDR]] to i32 addrspace(1)*
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; OPT-NEXT: [[VAL:%.*]] = call i32 @llvm.amdgcn.global.atomic.csub.p1i32(i32 addrspace(1)* [[TMP1]], i32 2)
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; OPT-NEXT: br label [[ENDIF]]
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; OPT: endif:
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; OPT-NEXT: [[X:%.*]] = phi i32 [ [[VAL]], [[IF]] ], [ 0, [[ENTRY:%.*]] ]
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; OPT-NEXT: store i32 [[X]], i32 addrspace(1)* [[OUT_GEP]], align 4
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; OPT-NEXT: ret void
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;
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; GCN-LABEL: test_sink_small_offset_global_atomic_csub_i32:
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; GCN: ; %bb.0: ; %entry
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; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
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; GCN-NEXT: v_mbcnt_lo_u32_b32 v0, -1, 0
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; GCN-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
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; GCN-NEXT: v_mov_b32_e32 v0, 0
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; GCN-NEXT: s_and_saveexec_b32 s4, vcc_lo
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; GCN-NEXT: s_cbranch_execz BB0_2
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; GCN-NEXT: ; %bb.1: ; %if
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; GCN-NEXT: v_mov_b32_e32 v0, 0
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; GCN-NEXT: v_mov_b32_e32 v1, 2
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: global_atomic_csub v0, v0, v1, s[2:3] offset:28 glc
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; GCN-NEXT: BB0_2: ; %endif
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; GCN-NEXT: s_or_b32 exec_lo, exec_lo, s4
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; GCN-NEXT: v_mov_b32_e32 v1, 0x3d0800
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; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)
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; GCN-NEXT: global_store_dword v1, v0, s[0:1] offset:252
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; GCN-NEXT: s_endpgm
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entry:
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%out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 999999
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%in.gep = getelementptr i32, i32 addrspace(1)* %in, i32 7
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%tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0
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%cmp = icmp eq i32 %tid, 0
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br i1 %cmp, label %endif, label %if
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if:
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%val = call i32 @llvm.amdgcn.global.atomic.csub.p1i32(i32 addrspace(1)* %in.gep, i32 2)
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br label %endif
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endif:
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%x = phi i32 [ %val, %if ], [ 0, %entry ]
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store i32 %x, i32 addrspace(1)* %out.gep
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br label %done
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done:
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ret void
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}
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declare i32 @llvm.amdgcn.global.atomic.csub.p1i32(i32 addrspace(1)* nocapture, i32) #0
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declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #1
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attributes #0 = { argmemonly nounwind }
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attributes #1 = { nounwind readnone willreturn }
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attributes #2 = { argmemonly nounwind willreturn }
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