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828db82d6d
This reverts r227987 "R600/SI: Determine target-specific encoding of READLANE and WRITELANE early v2". All the codegen changes are caused by the post-RA scheduler no longer treating readlane/writelane as scheduling barriers due to having unmodelled side effects. (The pseudos are hasSideEffects = 0, but the real instructions are hasSideEffects = ? which TableGen conservatively treats as 1.) Differential Revision: https://reviews.llvm.org/D90401
16 lines
543 B
LLVM
16 lines
543 B
LLVM
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -o - %s | FileCheck -check-prefix=GFX10 %s
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; Make sure new higher SGPRs are callee saved
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; GFX10-LABEL: {{^}}callee_new_sgprs:
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; GFX10: v_writelane_b32 v0, s104, 0
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; GFX10-DAG: v_writelane_b32 v0, s105, 1
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; GFX10-DAG: ; clobber s104
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; GFX10: ; clobber s105
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; GFX10: v_readlane_b32 s105, v0, 1
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; GFX10: v_readlane_b32 s104, v0, 0
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define void @callee_new_sgprs() {
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call void asm sideeffect "; clobber s104", "~{s104}"()
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call void asm sideeffect "; clobber s105", "~{s105}"()
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ret void
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}
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