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10fe28f702
Summary: This fixes some tests that did not specify -mcpu. Doing that disables all subtarget features, which gives behavior that (a) does not necessarily correspond to any actual target, and (b) can change as we add new subtarget features. Also added gfx1010 to memtime test. Differential Revision: https://reviews.llvm.org/D74594 Change-Id: I8c0fe4fa03e9a93ef8bb722cd42d22e064526309
44 lines
2.1 KiB
LLVM
44 lines
2.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -S -mtriple=amdgcn-- -mcpu=tonga -amdgpu-codegenprepare %s | FileCheck %s
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define amdgpu_kernel void @divrem24_assume(i32 addrspace(1)* %arg, i32 %arg1) {
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; CHECK-LABEL: @divrem24_assume(
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; CHECK-NEXT: bb:
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; CHECK-NEXT: [[TMP:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x(), !range !0
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; CHECK-NEXT: [[TMP2:%.*]] = icmp ult i32 [[ARG1:%.*]], 42
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; CHECK-NEXT: tail call void @llvm.assume(i1 [[TMP2]])
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; CHECK-NEXT: [[TMP0:%.*]] = uitofp i32 [[TMP]] to float
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; CHECK-NEXT: [[TMP1:%.*]] = uitofp i32 [[ARG1]] to float
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; CHECK-NEXT: [[TMP2:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[TMP1]])
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; CHECK-NEXT: [[TMP3:%.*]] = fmul fast float [[TMP0]], [[TMP2]]
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; CHECK-NEXT: [[TMP4:%.*]] = call fast float @llvm.trunc.f32(float [[TMP3]])
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; CHECK-NEXT: [[TMP5:%.*]] = fneg fast float [[TMP4]]
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; CHECK-NEXT: [[TMP6:%.*]] = call fast float @llvm.amdgcn.fmad.ftz.f32(float [[TMP5]], float [[TMP1]], float [[TMP0]])
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; CHECK-NEXT: [[TMP7:%.*]] = fptoui float [[TMP4]] to i32
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; CHECK-NEXT: [[TMP8:%.*]] = call fast float @llvm.fabs.f32(float [[TMP6]])
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; CHECK-NEXT: [[TMP9:%.*]] = call fast float @llvm.fabs.f32(float [[TMP1]])
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; CHECK-NEXT: [[TMP10:%.*]] = fcmp fast oge float [[TMP8]], [[TMP9]]
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; CHECK-NEXT: [[TMP11:%.*]] = select i1 [[TMP10]], i32 1, i32 0
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; CHECK-NEXT: [[TMP12:%.*]] = add i32 [[TMP7]], [[TMP11]]
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; CHECK-NEXT: [[TMP13:%.*]] = and i32 [[TMP12]], 1023
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; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[TMP13]] to i64
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; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, i32 addrspace(1)* [[ARG:%.*]], i64 [[TMP4]]
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; CHECK-NEXT: store i32 0, i32 addrspace(1)* [[TMP5]], align 4
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; CHECK-NEXT: ret void
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;
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bb:
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%tmp = tail call i32 @llvm.amdgcn.workitem.id.x(), !range !0
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%tmp2 = icmp ult i32 %arg1, 42
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tail call void @llvm.assume(i1 %tmp2)
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%tmp3 = udiv i32 %tmp, %arg1
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%tmp4 = zext i32 %tmp3 to i64
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%tmp5 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 %tmp4
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store i32 0, i32 addrspace(1)* %tmp5, align 4
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ret void
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}
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declare void @llvm.assume(i1)
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declare i32 @llvm.amdgcn.workitem.id.x()
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!0 = !{i32 0, i32 1024}
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