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https://github.com/RPCS3/llvm-mirror.git
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a76ecb87cf
- Add target id support (https://clang.llvm.org/docs/ClangOffloadBundler.html#target-id) - Add code object v4 support (https://llvm.org/docs/AMDGPUUsage.html#elf-code-object) - Add kernarg_size to kernel descriptor - Change trap handler ABI to no longer move queue pointer into s[0:1] - Cleanup ELF definitions - Add V2, V3, V4 suffixes to make a clear distinction for code object version - Consolidate note names Differential Revision: https://reviews.llvm.org/D95638
147 lines
4.7 KiB
LLVM
147 lines
4.7 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=GCN %s
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; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-xnack -verify-machineinstrs < %s | FileCheck -check-prefix=VI-NOXNACK -check-prefix=GCN %s
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; RUN: llc -march=amdgcn -mcpu=carrizo -mattr=-xnack -verify-machineinstrs < %s | FileCheck -check-prefixes=VI-NOXNACK,GCN %s
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; RUN: llc -march=amdgcn -mcpu=stoney -mattr=-xnack -verify-machineinstrs < %s | FileCheck -check-prefixes=VI-NOXNACK,GCN %s
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; RUN: llc -march=amdgcn -mcpu=carrizo -mattr=+xnack -verify-machineinstrs < %s | FileCheck -check-prefix=VI-XNACK -check-prefix=GCN %s
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; RUN: llc -march=amdgcn -mcpu=stoney -mattr=+xnack -verify-machineinstrs < %s | FileCheck -check-prefix=VI-XNACK -check-prefix=GCN %s
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; RUN: llc -march=amdgcn -mtriple=amdgcn--amdhsa -mcpu=kaveri --amdhsa-code-object-version=2 -verify-machineinstrs < %s | FileCheck -check-prefixes=CI,HSA-CI-V2,GCN %s
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; RUN: llc -march=amdgcn -mtriple=amdgcn--amdhsa -mcpu=carrizo --amdhsa-code-object-version=2 -mattr=+xnack -verify-machineinstrs < %s | FileCheck -check-prefixes=VI-XNACK,HSA-VI-XNACK-V2,GCN %s
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; RUN: llc -march=amdgcn -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN %s
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; RUN: llc -march=amdgcn -mtriple=amdgcn--amdhsa -mcpu=carrizo -mattr=-xnack -verify-machineinstrs < %s | FileCheck -check-prefixes=VI-NOXNACK,HSA-VI-NOXNACK,GCN %s
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; RUN: llc -march=amdgcn -mtriple=amdgcn--amdhsa -mcpu=carrizo -mattr=+xnack -verify-machineinstrs < %s | FileCheck -check-prefixes=VI-XNACK,HSA-VI-XNACK,GCN %s
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; GCN-LABEL: {{^}}no_vcc_no_flat:
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; HSA-CI-V2: is_xnack_enabled = 0
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; HSA-VI-XNACK-V2: is_xnack_enabled = 1
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; NOT-HSA-CI: .amdhsa_reserve_xnack_mask
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; HSA-VI-NOXNACK: .amdhsa_reserve_xnack_mask 0
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; HSA-VI-XNACK: .amdhsa_reserve_xnack_mask 1
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; CI: ; NumSgprs: 8
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; VI-NOXNACK: ; NumSgprs: 8
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; VI-XNACK: ; NumSgprs: 12
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define amdgpu_kernel void @no_vcc_no_flat() {
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entry:
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call void asm sideeffect "", "~{s7}"()
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ret void
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}
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; GCN-LABEL: {{^}}vcc_no_flat:
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; HSA-CI-V2: is_xnack_enabled = 0
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; HSA-VI-XNACK-V2: is_xnack_enabled = 1
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; NOT-HSA-CI: .amdhsa_reserve_xnack_mask
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; HSA-VI-NOXNACK: .amdhsa_reserve_xnack_mask 0
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; HSA-VI-XNACK: .amdhsa_reserve_xnack_mask 1
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; CI: ; NumSgprs: 10
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; VI-NOXNACK: ; NumSgprs: 10
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; VI-XNACK: ; NumSgprs: 12
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define amdgpu_kernel void @vcc_no_flat() {
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entry:
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call void asm sideeffect "", "~{s7},~{vcc}"()
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ret void
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}
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; GCN-LABEL: {{^}}no_vcc_flat:
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; HSA-CI-V2: is_xnack_enabled = 0
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; HSA-VI-XNACK-V2: is_xnack_enabled = 1
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; NOT-HSA-CI: .amdhsa_reserve_xnack_mask
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; HSA-VI-NOXNACK: .amdhsa_reserve_xnack_mask 0
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; HSA-VI-XNACK: .amdhsa_reserve_xnack_mask 1
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; CI: ; NumSgprs: 12
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; VI-NOXNACK: ; NumSgprs: 14
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; VI-XNACK: ; NumSgprs: 14
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define amdgpu_kernel void @no_vcc_flat() {
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entry:
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call void asm sideeffect "", "~{s7},~{flat_scratch}"()
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ret void
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}
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; GCN-LABEL: {{^}}vcc_flat:
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; HSA-CI-V2: is_xnack_enabled = 0
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; HSA-VI-XNACK-V2: is_xnack_enabled = 1
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; NOT-HSA-CI: .amdhsa_reserve_xnack_mask
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; HSA-VI-NOXNACK: .amdhsa_reserve_xnack_mask 0
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; HSA-VI-XNACK: .amdhsa_reserve_xnack_mask 1
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; CI: ; NumSgprs: 12
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; VI-NOXNACK: ; NumSgprs: 14
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; VI-XNACK: ; NumSgprs: 14
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define amdgpu_kernel void @vcc_flat() {
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entry:
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call void asm sideeffect "", "~{s7},~{vcc},~{flat_scratch}"()
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ret void
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}
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; Make sure used SGPR count for flat_scr is correct when there is no
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; scratch usage and implicit flat uses.
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; GCN-LABEL: {{^}}use_flat_scr:
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; HSA-CI-V2: is_xnack_enabled = 0
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; HSA-VI-XNACK-V2: is_xnack_enabled = 1
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; NOT-HSA-CI: .amdhsa_reserve_xnack_mask
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; HSA-VI-NOXNACK: .amdhsa_reserve_xnack_mask 0
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; HSA-VI-XNACK: .amdhsa_reserve_xnack_mask 1
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; CI: NumSgprs: 4
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; VI-NOXNACK: NumSgprs: 6
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; VI-XNACK: NumSgprs: 6
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define amdgpu_kernel void @use_flat_scr() #0 {
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entry:
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call void asm sideeffect "; clobber ", "~{flat_scratch}"()
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ret void
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}
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; GCN-LABEL: {{^}}use_flat_scr_lo:
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; HSA-CI-V2: is_xnack_enabled = 0
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; HSA-VI-XNACK-V2: is_xnack_enabled = 1
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; NOT-HSA-CI: .amdhsa_reserve_xnack_mask
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; HSA-VI-NOXNACK: .amdhsa_reserve_xnack_mask 0
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; HSA-VI-XNACK: .amdhsa_reserve_xnack_mask 1
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; CI: NumSgprs: 4
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; VI-NOXNACK: NumSgprs: 6
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; VI-XNACK: NumSgprs: 6
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define amdgpu_kernel void @use_flat_scr_lo() #0 {
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entry:
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call void asm sideeffect "; clobber ", "~{flat_scratch_lo}"()
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ret void
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}
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; GCN-LABEL: {{^}}use_flat_scr_hi:
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; HSA-CI-V2: is_xnack_enabled = 0
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; HSA-VI-XNACK-V2: is_xnack_enabled = 1
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; NOT-HSA-CI: .amdhsa_reserve_xnack_mask
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; HSA-VI-NOXNACK: .amdhsa_reserve_xnack_mask 0
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; HSA-VI-XNACK: .amdhsa_reserve_xnack_mask 1
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; CI: NumSgprs: 4
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; VI-NOXNACK: NumSgprs: 6
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; VI-XNACK: NumSgprs: 6
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define amdgpu_kernel void @use_flat_scr_hi() #0 {
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entry:
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call void asm sideeffect "; clobber ", "~{flat_scratch_hi}"()
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ret void
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}
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attributes #0 = { nounwind }
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