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c22abcde1d
Use the 64-bit SGPR base with a 0 offset, since it's 1 fewer instruction to materialize the 0 vs. the 64-bit copy.
39 lines
1.7 KiB
LLVM
39 lines
1.7 KiB
LLVM
; RUN: llc < %s -march=amdgcn -mcpu=gfx1030 -verify-machineinstrs | FileCheck %s -check-prefix=GCN
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; RUN: llc < %s -march=amdgcn -mcpu=gfx1031 -verify-machineinstrs | FileCheck %s -check-prefix=GCN
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declare i32 @llvm.amdgcn.buffer.atomic.csub(i32, <4 x i32>, i32, i32, i1)
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declare i32 @llvm.amdgcn.global.atomic.csub(i32 addrspace(1)*, i32)
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; GCN-LABEL: {{^}}buffer_atomic_csub:
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; GCN: buffer_atomic_csub v0, v1, s[0:3], 0 idxen glc
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define amdgpu_ps void @buffer_atomic_csub(<4 x i32> inreg %rsrc, i32 %data, i32 %vindex) {
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main_body:
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%ret = call i32 @llvm.amdgcn.buffer.atomic.csub(i32 %data, <4 x i32> %rsrc, i32 %vindex, i32 0, i1 0)
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ret void
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}
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; GCN-LABEL: {{^}}buffer_atomic_csub_off4_slc:
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; GCN: buffer_atomic_csub v0, v1, s[0:3], 0 idxen offset:4 glc slc
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define amdgpu_ps void @buffer_atomic_csub_off4_slc(<4 x i32> inreg %rsrc, i32 %data, i32 %vindex) {
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main_body:
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%ret = call i32 @llvm.amdgcn.buffer.atomic.csub(i32 %data, <4 x i32> %rsrc, i32 %vindex, i32 4, i1 1)
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ret void
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}
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; GCN-LABEL: {{^}}global_atomic_csub:
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; GCN: global_atomic_csub v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9:]+}}, s{{\[[0-9]+:[0-9]+\]}} glc
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define amdgpu_kernel void @global_atomic_csub(i32 addrspace(1)* %ptr, i32 %data) {
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main_body:
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%ret = call i32 @llvm.amdgcn.global.atomic.csub(i32 addrspace(1)* %ptr, i32 %data)
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ret void
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}
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; GCN-LABEL: {{^}}global_atomic_csub_off4:
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; GCN: global_atomic_csub v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}} offset:4 glc
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define amdgpu_kernel void @global_atomic_csub_off4(i32 addrspace(1)* %ptr, i32 %data) {
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main_body:
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%p = getelementptr i32, i32 addrspace(1)* %ptr, i64 1
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%ret = call i32 @llvm.amdgcn.global.atomic.csub(i32 addrspace(1)* %p, i32 %data)
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ret void
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}
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