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b2cdcb043a
Summary: Add patterns to select s_cselect in the isel. Handle more cases of implicit SCC accesses in si-fix-sgpr-copies to allow new patterns to work. Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, asbirlea, kerbowa, llvm-commits Tags: #llvm Re-commit D81925 with a bugfix D82370. Differential Revision: https://reviews.llvm.org/D81925 Differential Revision: https://reviews.llvm.org/D82370
32 lines
1.4 KiB
LLVM
32 lines
1.4 KiB
LLVM
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=tonga -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
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; FIXME: This should go in existing select.ll test, except the current testcase there is broken on GCN
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; GCN-LABEL: {{^}}select_i1:
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; GCN: v_cndmask_b32
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; GCN-NOT: v_cndmask_b32
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define amdgpu_kernel void @select_i1(i1 addrspace(1)* %out, i32 %cond, i1 %a, i1 %b) nounwind {
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%cmp = icmp ugt i32 %cond, 5
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%sel = select i1 %cmp, i1 %a, i1 %b
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store i1 %sel, i1 addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}s_minmax_i1:
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; GCN: s_load_dword [[LOAD:s[0-9]+]],
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; GCN-DAG: s_lshr_b32 [[A:s[0-9]+]], [[LOAD]], 8
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; GCN-DAG: s_lshr_b32 [[B:s[0-9]+]], [[LOAD]], 16
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; GCN-DAG: s_and_b32 [[COND:s[0-9]+]], 1, [[LOAD]]
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; GCN: v_mov_b32_e32 [[V_B:v[0-9]+]], [[B]]
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; GCN: v_mov_b32_e32 [[V_A:v[0-9]+]], [[A]]
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; GCN: v_cmp_eq_u32_e64 vcc, [[COND]], 1
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; GCN: v_cndmask_b32_e32 [[SEL:v[0-9]+]], [[V_B]], [[V_A]]
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; GCN: v_and_b32_e32 v{{[0-9]+}}, 1, [[SEL]]
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define amdgpu_kernel void @s_minmax_i1(i1 addrspace(1)* %out, [8 x i32], i1 zeroext %cond, i1 zeroext %a, i1 zeroext %b) nounwind {
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%cmp = icmp slt i1 %cond, false
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%sel = select i1 %cmp, i1 %a, i1 %b
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store i1 %sel, i1 addrspace(1)* %out, align 4
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ret void
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}
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