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AMDGPU normally spills SGPRs to VGPRs. Previously, since all register classes are handled at the same time, this was problematic. We don't know ahead of time how many registers will be needed to be reserved to handle the spilling. If no VGPRs were left for spilling, we would have to try to spill to memory. If the spilled SGPRs were required for exec mask manipulation, it is highly problematic because the lanes active at the point of spill are not necessarily the same as at the restore point. Avoid this problem by fully allocating SGPRs in a separate regalloc run from VGPRs. This way we know the exact number of VGPRs needed, and can reserve them for a second run. This fixes the most serious issues, but it is still possible using inline asm to make all VGPRs unavailable. Start erroring in the case where we ever would require memory for an SGPR spill. This is implemented by giving each regalloc pass a callback which reports if a register class should be handled or not. A few passes need some small changes to deal with leftover virtual registers. In the AMDGPU implementation, a new pass is introduced to take the place of PrologEpilogInserter for SGPR spills emitted during the first run. One disadvantage of this is currently StackSlotColoring is no longer used for SGPR spills. It would need to be run again, which will require more work. Error if the standard -regalloc option is used. Introduce new separate -sgpr-regalloc and -vgpr-regalloc flags, so the two runs can be controlled individually. PBQB is not currently supported, so this also prevents using the unhandled allocator.
71 lines
2.5 KiB
YAML
71 lines
2.5 KiB
YAML
# RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs -amdgpu-dce-in-ra=0 -stress-regalloc=1 -start-before=simple-register-coalescing -stop-after=greedy,1 -o - %s | FileCheck %s
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# https://bugs.llvm.org/show_bug.cgi?id=33620
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---
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# This would assert due to the empty live interval created for %9
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# on the last S_NOP with an undef subreg use.
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# CHECK-LABEL: name: expecting_non_empty_interval
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# CHECK: undef %7.sub1:vreg_64 = V_MAC_F32_e32 0, undef %1:vgpr_32, undef %7.sub1, implicit $mode, implicit $exec
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# CHECK-NEXT: SI_SPILL_V64_SAVE %7, %stack.0, $sgpr32, 0, implicit $exec :: (store (s64) into %stack.0, align 4, addrspace 5)
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# CHECK-NEXT: undef %5.sub1:vreg_64 = V_MOV_B32_e32 1786773504, implicit $exec
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# CHECK-NEXT: dead %3:vgpr_32 = V_MUL_F32_e32 0, %5.sub1, implicit $mode, implicit $exec
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# CHECK: S_NOP 0, implicit %6.sub1
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# CHECK-NEXT: %8:vreg_64 = SI_SPILL_V64_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load (s64) from %stack.0, align 4, addrspace 5)
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# CHECK-NEXT: S_NOP 0, implicit %8.sub1
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# CHECK-NEXT: S_NOP 0, implicit undef %9.sub0
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name: expecting_non_empty_interval
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tracksRegLiveness: true
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machineFunctionInfo:
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scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3
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stackPtrOffsetReg: $sgpr32
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body: |
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bb.0:
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successors: %bb.1
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undef %0.sub1:vreg_64 = V_MAC_F32_e32 0, undef %1:vgpr_32, undef %0.sub1, implicit $mode, implicit $exec
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undef %2.sub1:vreg_64 = V_MOV_B32_e32 1786773504, implicit $exec
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dead %3:vgpr_32 = V_MUL_F32_e32 0, %2.sub1, implicit $mode, implicit $exec
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bb.1:
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S_NOP 0, implicit %2.sub1
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S_NOP 0, implicit %0.sub1
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S_NOP 0, implicit undef %0.sub0
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...
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# Similar assert which happens when trying to rematerialize.
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# https://bugs.llvm.org/show_bug.cgi?id=33884
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---
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# CHECK-LABEL: name: rematerialize_empty_interval_has_reference
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# CHECK-NOT: MOV
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# CHECK: undef %1.sub2:vreg_128 = V_MOV_B32_e32 1786773504, implicit $exec
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# CHECK: bb.1:
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# CHECK-NEXT: S_NOP 0, implicit %1.sub2
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# CHECK-NEXT: S_NOP 0, implicit undef %4.sub0
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# CHECK-NEXT: undef %2.sub2:vreg_128 = V_MOV_B32_e32 0, implicit $exec
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# CHECK-NEXT: S_NOP 0, implicit %2.sub2
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name: rematerialize_empty_interval_has_reference
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tracksRegLiveness: true
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machineFunctionInfo:
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scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3
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stackPtrOffsetReg: $sgpr32
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body: |
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bb.0:
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successors: %bb.1
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undef %0.sub2:vreg_128 = V_MOV_B32_e32 0, implicit $exec
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undef %1.sub2:vreg_128 = V_MOV_B32_e32 1786773504, implicit $exec
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bb.1:
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S_NOP 0, implicit %1.sub2
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S_NOP 0, implicit undef %0.sub0
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S_NOP 0, implicit %0.sub2
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...
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